/**
 * *****************************************************************
 * @file    rfc_ctype_map.h
 * @author  WuHao(hwu@andartechs.com.cn)
 * @version 1.0.0
 * @date    2020-11-24
 * @brief   rfc configuration registers address definition
 *
 *                 Copyright (c) 2020, Andar Technologies Inc.
 *                           www.andartechs.com 
 *
 * *****************************************************************
 */
#ifndef RFC__MAP__H
#define RFC__MAP__H
/*!
**********************************************************
* \brief
*    rfc configuration registers address definition
* \author
*    generated by reg_table automatically,dont modify it
**********************************************************
*/
#include "adt3102_type_define.h"
//#define rf_atn0_reg 0x000
#define rf_atn0_reg_atn0_shift 0
#define rf_atn0_reg_atn0_mask ((1<<5)-1)

//#define rf_psr0_reg 0x001
#define rf_psr0_reg_psr0_shift 0
#define rf_psr0_reg_psr0_mask ((1<<6)-1)

//#define rf_atn1_reg 0x002
#define rf_atn1_reg_atn1_shift 0
#define rf_atn1_reg_atn1_mask ((1<<5)-1)

//#define rf_psr1_reg 0x003
#define rf_psr1_reg_psr1_shift 0
#define rf_psr1_reg_psr1_mask ((1<<6)-1)

//#define rf_atn2_reg 0x004
#define rf_atn2_reg_atn2_shift 0
#define rf_atn2_reg_atn2_mask ((1<<5)-1)

//#define rf_psr2_reg 0x005
#define rf_psr2_reg_psr2_shift 0
#define rf_psr2_reg_psr2_mask ((1<<6)-1)

//#define rf_atn3_reg 0x006
#define rf_atn3_reg_atn3_shift 0
#define rf_atn3_reg_atn3_mask ((1<<5)-1)

//#define rf_psr3_reg 0x007
#define rf_psr3_reg_psr3_shift 0
#define rf_psr3_reg_psr3_mask ((1<<6)-1)

//#define rf_atn4_reg 0x008
#define rf_atn4_reg_atn4_shift 0
#define rf_atn4_reg_atn4_mask ((1<<5)-1)

//#define rf_psr4_reg 0x009
#define rf_psr4_reg_psr4_shift 0
#define rf_psr4_reg_psr4_mask ((1<<6)-1)

//#define rf_atn5_reg 0x00a
#define rf_atn5_reg_atn5_shift 0
#define rf_atn5_reg_atn5_mask ((1<<5)-1)

//#define rf_psr5_reg 0x00b
#define rf_psr5_reg_psr5_shift 0
#define rf_psr5_reg_psr5_mask ((1<<6)-1)

//#define rf_atn6_reg 0x00c
#define rf_atn6_reg_atn6_shift 0
#define rf_atn6_reg_atn6_mask ((1<<5)-1)

//#define rf_psr6_reg 0x00d
#define rf_psr6_reg_psr6_shift 0
#define rf_psr6_reg_psr6_mask ((1<<6)-1)

//#define rf_atn7_reg 0x00e
#define rf_atn7_reg_atn7_shift 0
#define rf_atn7_reg_atn7_mask ((1<<5)-1)

//#define rf_psr7_reg 0x00f
#define rf_psr7_reg_psr7_shift 0
#define rf_psr7_reg_psr7_mask ((1<<6)-1)

//#define rf_atn8_reg 0x010
#define rf_atn8_reg_atn8_shift 0
#define rf_atn8_reg_atn8_mask ((1<<5)-1)

//#define rf_psr8_reg 0x011
#define rf_psr8_reg_psr8_shift 0
#define rf_psr8_reg_psr8_mask ((1<<6)-1)

//#define rf_atn9_reg 0x012
#define rf_atn9_reg_atn9_shift 0
#define rf_atn9_reg_atn9_mask ((1<<5)-1)

//#define rf_psr9_reg 0x013
#define rf_psr9_reg_psr9_shift 0
#define rf_psr9_reg_psr9_mask ((1<<6)-1)

//#define rf_atn10_reg 0x014
#define rf_atn10_reg_atn10_shift 0
#define rf_atn10_reg_atn10_mask ((1<<5)-1)

//#define rf_psr10_reg 0x015
#define rf_psr10_reg_psr10_shift 0
#define rf_psr10_reg_psr10_mask ((1<<6)-1)

//#define rf_atn11_reg 0x016
#define rf_atn11_reg_atn11_shift 0
#define rf_atn11_reg_atn11_mask ((1<<5)-1)

//#define rf_psr11_reg 0x017
#define rf_psr11_reg_psr11_shift 0
#define rf_psr11_reg_psr11_mask ((1<<6)-1)

//#define rf_atn12_reg 0x018
#define rf_atn12_reg_atn12_shift 0
#define rf_atn12_reg_atn12_mask ((1<<5)-1)

//#define rf_psr12_reg 0x019
#define rf_psr12_reg_psr12_shift 0
#define rf_psr12_reg_psr12_mask ((1<<6)-1)

//#define rf_atn13_reg 0x01a
#define rf_atn13_reg_atn13_shift 0
#define rf_atn13_reg_atn13_mask ((1<<5)-1)

//#define rf_psr13_reg 0x01b
#define rf_psr13_reg_psr13_shift 0
#define rf_psr13_reg_psr13_mask ((1<<6)-1)

//#define rf_atn14_reg 0x01c
#define rf_atn14_reg_atn14_shift 0
#define rf_atn14_reg_atn14_mask ((1<<5)-1)

//#define rf_psr14_reg 0x01d
#define rf_psr14_reg_psr14_shift 0
#define rf_psr14_reg_psr14_mask ((1<<6)-1)

//#define rf_atn15_reg 0x01e
#define rf_atn15_reg_atn15_shift 0
#define rf_atn15_reg_atn15_mask ((1<<5)-1)

//#define rf_psr15_reg 0x01f
#define rf_psr15_reg_psr15_shift 0
#define rf_psr15_reg_psr15_mask ((1<<6)-1)

//#define rfc_nload_reg 0x020
#define rfc_nload_reg_ps_rstn_inv_bit (1<<3)
#define rfc_nload_reg_ps1_en_inv_bit (1<<2)
#define rfc_nload_reg_ps0_en_inv_bit (1<<1)
#define rfc_nload_reg_nload_inv_bit (1<<0)

//#define rf_atn_all_reg 0x023
#define rf_atn_all_reg_atn_all_ch_en_bit (1<<5)
#define rf_atn_all_reg_atn_all_ch_shift 0
#define rf_atn_all_reg_atn_all_ch_mask ((1<<5)-1)

//#define rf_psr_all_reg 0x024
#define rf_psr_all_reg_psr_all_ch_en_bit (1<<6)
#define rf_psr_all_reg_psr_all_ch_shift 0
#define rf_psr_all_reg_psr_all_ch_mask ((1<<6)-1)

//#define rf_gpadc_data_reg 0x035
#define rf_gpadc_data_reg_gpadc_data_shift 0
#define rf_gpadc_data_reg_gpadc_data_mask ((1<<8)-1)

//#define rf_gpadc_reg_reg 0x036
#define rf_gpadc_reg_reg_gpadc_reg3_shift 16
#define rf_gpadc_reg_reg_gpadc_reg3_mask ((1<<8)-1)
#define rf_gpadc_reg_reg_gpadc_reg2_shift 8
#define rf_gpadc_reg_reg_gpadc_reg2_mask ((1<<8)-1)
#define rf_gpadc_reg_reg_gpadc_reg1_shift 0
#define rf_gpadc_reg_reg_gpadc_reg1_mask ((1<<8)-1)

//#define rf_adc0_data_reg 0x037
#define rf_adc0_data_reg_adc0_qdata_shift 12
#define rf_adc0_data_reg_adc0_qdata_mask ((1<<12)-1)
#define rf_adc0_data_reg_adc0_idata_shift 0
#define rf_adc0_data_reg_adc0_idata_mask ((1<<12)-1)

//#define rf_adc0_regs_reg 0x038
#define rf_adc0_regs_reg_bb_atb_sel_shift 19
#define rf_adc0_regs_reg_bb_atb_sel_mask ((1<<4)-1)
#define rf_adc0_regs_reg_adc0_atb_en_bit (1<<18)
#define rf_adc0_regs_reg_adc0_ref_en_bit (1<<17)
#define rf_adc0_regs_reg_adc0_sar_en_bit (1<<16)
#define rf_adc0_regs_reg_adc0_reg2_shift 8
#define rf_adc0_regs_reg_adc0_reg2_mask ((1<<8)-1)
#define rf_adc0_regs_reg_adc0_reg1_shift 0
#define rf_adc0_regs_reg_adc0_reg1_mask ((1<<8)-1)

//#define rf_adc1_data_reg 0x03d
#define rf_adc1_data_reg_adc1_qdata_shift 12
#define rf_adc1_data_reg_adc1_qdata_mask ((1<<12)-1)
#define rf_adc1_data_reg_adc1_idata_shift 0
#define rf_adc1_data_reg_adc1_idata_mask ((1<<12)-1)

//#define rf_adc1_regs_reg 0x03e
#define rf_adc1_regs_reg_adc1_atb_en_bit (1<<18)
#define rf_adc1_regs_reg_adc1_ref_en_bit (1<<17)
#define rf_adc1_regs_reg_adc1_sar_en_bit (1<<16)
#define rf_adc1_regs_reg_adc1_reg2_shift 8
#define rf_adc1_regs_reg_adc1_reg2_mask ((1<<8)-1)
#define rf_adc1_regs_reg_adc1_reg1_shift 0
#define rf_adc1_regs_reg_adc1_reg1_mask ((1<<8)-1)

//#define rf_bias1_en_reg 0x042
#define rf_bias1_en_reg_bias1_en_shift 0
#define rf_bias1_en_reg_bias1_en_mask ((1<<12)-1)

//#define rf_rc32k_reg_reg 0x043
#define rf_rc32k_reg_reg_rc32k_reg_shift 0
#define rf_rc32k_reg_reg_rc32k_reg_mask ((1<<8)-1)

//#define rf_bias1_regs_reg 0x044
#define rf_bias1_regs_reg_bias1_reg2_shift 8
#define rf_bias1_regs_reg_bias1_reg2_mask ((1<<8)-1)
#define rf_bias1_regs_reg_bias1_reg1_shift 0
#define rf_bias1_regs_reg_bias1_reg1_mask ((1<<8)-1)

//#define rfc_bias1_dina_reg 0x045
#define rfc_bias1_dina_reg_bias1_din7_shift 28
#define rfc_bias1_dina_reg_bias1_din7_mask ((1<<4)-1)
#define rfc_bias1_dina_reg_bias1_din6_shift 24
#define rfc_bias1_dina_reg_bias1_din6_mask ((1<<4)-1)
#define rfc_bias1_dina_reg_bias1_din5_shift 20
#define rfc_bias1_dina_reg_bias1_din5_mask ((1<<4)-1)
#define rfc_bias1_dina_reg_bias1_din4_shift 16
#define rfc_bias1_dina_reg_bias1_din4_mask ((1<<4)-1)
#define rfc_bias1_dina_reg_bias1_din3_shift 12
#define rfc_bias1_dina_reg_bias1_din3_mask ((1<<4)-1)
#define rfc_bias1_dina_reg_bias1_din2_shift 8
#define rfc_bias1_dina_reg_bias1_din2_mask ((1<<4)-1)
#define rfc_bias1_dina_reg_bias1_din1_shift 4
#define rfc_bias1_dina_reg_bias1_din1_mask ((1<<4)-1)
#define rfc_bias1_dina_reg_bias1_din0_shift 0
#define rfc_bias1_dina_reg_bias1_din0_mask ((1<<4)-1)

//#define rf_bias1_dinb_reg 0x046
#define rf_bias1_dinb_reg_bias1_din15_shift 28
#define rf_bias1_dinb_reg_bias1_din15_mask ((1<<4)-1)
#define rf_bias1_dinb_reg_bias1_din14_shift 24
#define rf_bias1_dinb_reg_bias1_din14_mask ((1<<4)-1)
#define rf_bias1_dinb_reg_bias1_din13_shift 20
#define rf_bias1_dinb_reg_bias1_din13_mask ((1<<4)-1)
#define rf_bias1_dinb_reg_bias1_din12_shift 16
#define rf_bias1_dinb_reg_bias1_din12_mask ((1<<4)-1)
#define rf_bias1_dinb_reg_bias1_din11_shift 12
#define rf_bias1_dinb_reg_bias1_din11_mask ((1<<4)-1)
#define rf_bias1_dinb_reg_bias1_din10_shift 8
#define rf_bias1_dinb_reg_bias1_din10_mask ((1<<4)-1)
#define rf_bias1_dinb_reg_bias1_din9_shift 4
#define rf_bias1_dinb_reg_bias1_din9_mask ((1<<4)-1)
#define rf_bias1_dinb_reg_bias1_din8_shift 0
#define rf_bias1_dinb_reg_bias1_din8_mask ((1<<4)-1)

//#define rf_bias1_dinc_reg 0x047
#define rf_bias1_dinc_reg_bias1_din23_shift 28
#define rf_bias1_dinc_reg_bias1_din23_mask ((1<<4)-1)
#define rf_bias1_dinc_reg_bias1_din22_shift 24
#define rf_bias1_dinc_reg_bias1_din22_mask ((1<<4)-1)
#define rf_bias1_dinc_reg_bias1_din21_shift 20
#define rf_bias1_dinc_reg_bias1_din21_mask ((1<<4)-1)
#define rf_bias1_dinc_reg_bias1_din20_shift 16
#define rf_bias1_dinc_reg_bias1_din20_mask ((1<<4)-1)
#define rf_bias1_dinc_reg_bias1_din19_shift 12
#define rf_bias1_dinc_reg_bias1_din19_mask ((1<<4)-1)
#define rf_bias1_dinc_reg_bias1_din18_shift 8
#define rf_bias1_dinc_reg_bias1_din18_mask ((1<<4)-1)
#define rf_bias1_dinc_reg_bias1_din17_shift 4
#define rf_bias1_dinc_reg_bias1_din17_mask ((1<<4)-1)
#define rf_bias1_dinc_reg_bias1_din16_shift 0
#define rf_bias1_dinc_reg_bias1_din16_mask ((1<<4)-1)

//#define rf_bias2_regs_reg 0x048
#define rf_bias2_regs_reg_bias2_en_bit (1<<8)
#define rf_bias2_regs_reg_bias2_reg1_shift 0
#define rf_bias2_regs_reg_bias2_reg1_mask ((1<<8)-1)

//#define rf_bias2_dina_reg 0x04b
#define rf_bias2_dina_reg_bias2_din7_shift 28
#define rf_bias2_dina_reg_bias2_din7_mask ((1<<4)-1)
#define rf_bias2_dina_reg_bias2_din6_shift 24
#define rf_bias2_dina_reg_bias2_din6_mask ((1<<4)-1)
#define rf_bias2_dina_reg_bias2_din5_shift 20
#define rf_bias2_dina_reg_bias2_din5_mask ((1<<4)-1)
#define rf_bias2_dina_reg_bias2_din4_shift 16
#define rf_bias2_dina_reg_bias2_din4_mask ((1<<4)-1)
#define rf_bias2_dina_reg_bias2_din3_shift 12
#define rf_bias2_dina_reg_bias2_din3_mask ((1<<4)-1)
#define rf_bias2_dina_reg_bias2_din2_shift 8
#define rf_bias2_dina_reg_bias2_din2_mask ((1<<4)-1)
#define rf_bias2_dina_reg_bias2_din1_shift 4
#define rf_bias2_dina_reg_bias2_din1_mask ((1<<4)-1)
#define rf_bias2_dina_reg_bias2_din0_shift 0
#define rf_bias2_dina_reg_bias2_din0_mask ((1<<4)-1)

//#define rf_bias2_dinb_reg 0x04c
#define rf_bias2_dinb_reg_bias2_din15_shift 28
#define rf_bias2_dinb_reg_bias2_din15_mask ((1<<4)-1)
#define rf_bias2_dinb_reg_bias2_din14_shift 24
#define rf_bias2_dinb_reg_bias2_din14_mask ((1<<4)-1)
#define rf_bias2_dinb_reg_bias2_din13_shift 20
#define rf_bias2_dinb_reg_bias2_din13_mask ((1<<4)-1)
#define rf_bias2_dinb_reg_bias2_din12_shift 16
#define rf_bias2_dinb_reg_bias2_din12_mask ((1<<4)-1)
#define rf_bias2_dinb_reg_bias2_din11_shift 12
#define rf_bias2_dinb_reg_bias2_din11_mask ((1<<4)-1)
#define rf_bias2_dinb_reg_bias2_din10_shift 8
#define rf_bias2_dinb_reg_bias2_din10_mask ((1<<4)-1)
#define rf_bias2_dinb_reg_bias2_din9_shift 4
#define rf_bias2_dinb_reg_bias2_din9_mask ((1<<4)-1)
#define rf_bias2_dinb_reg_bias2_din8_shift 0
#define rf_bias2_dinb_reg_bias2_din8_mask ((1<<4)-1)

//#define rf_bias2_dinc_reg 0x04d
#define rf_bias2_dinc_reg_bias2_din19_shift 12
#define rf_bias2_dinc_reg_bias2_din19_mask ((1<<4)-1)
#define rf_bias2_dinc_reg_bias2_din18_shift 8
#define rf_bias2_dinc_reg_bias2_din18_mask ((1<<4)-1)
#define rf_bias2_dinc_reg_bias2_din17_shift 4
#define rf_bias2_dinc_reg_bias2_din17_mask ((1<<4)-1)
#define rf_bias2_dinc_reg_bias2_din16_shift 0
#define rf_bias2_dinc_reg_bias2_din16_mask ((1<<4)-1)

//#define rfc_xo50m_cfg_reg 0x054
#define rfc_xo50m_cfg_reg_xo50m_reg2_shift 4
#define rfc_xo50m_cfg_reg_xo50m_reg2_mask ((1<<8)-1)
#define rfc_xo50m_cfg_reg_xo50m_reg1_shift 0
#define rfc_xo50m_cfg_reg_xo50m_reg1_mask ((1<<4)-1)

//#define rf_plli_ldo_cfg_reg 0x055
#define rf_plli_ldo_cfg_reg_plli_bias_reg1_shift 8
#define rf_plli_ldo_cfg_reg_plli_bias_reg1_mask ((1<<4)-1)
#define rf_plli_ldo_cfg_reg_plli_ldo_reg1_shift 0
#define rf_plli_ldo_cfg_reg_plli_ldo_reg1_mask ((1<<8)-1)

//#define rf_plli_daca_reg 0x056
#define rf_plli_daca_reg_plli_dac8_reg_shift 28
#define rf_plli_daca_reg_plli_dac8_reg_mask ((1<<4)-1)
#define rf_plli_daca_reg_plli_dac7_reg_shift 24
#define rf_plli_daca_reg_plli_dac7_reg_mask ((1<<4)-1)
#define rf_plli_daca_reg_plli_dac6_reg_shift 20
#define rf_plli_daca_reg_plli_dac6_reg_mask ((1<<4)-1)
#define rf_plli_daca_reg_plli_dac5_reg_shift 16
#define rf_plli_daca_reg_plli_dac5_reg_mask ((1<<4)-1)
#define rf_plli_daca_reg_plli_dac4_reg_shift 12
#define rf_plli_daca_reg_plli_dac4_reg_mask ((1<<4)-1)
#define rf_plli_daca_reg_plli_dac3_reg_shift 8
#define rf_plli_daca_reg_plli_dac3_reg_mask ((1<<4)-1)
#define rf_plli_daca_reg_plli_dac2_reg_shift 4
#define rf_plli_daca_reg_plli_dac2_reg_mask ((1<<4)-1)
#define rf_plli_daca_reg_plli_dac1_reg_shift 0
#define rf_plli_daca_reg_plli_dac1_reg_mask ((1<<4)-1)

//#define rf_plli_dacb_reg 0x057
#define rf_plli_dacb_reg_plli_dac12_reg_shift 12
#define rf_plli_dacb_reg_plli_dac12_reg_mask ((1<<4)-1)
#define rf_plli_dacb_reg_plli_dac11_reg_shift 8
#define rf_plli_dacb_reg_plli_dac11_reg_mask ((1<<4)-1)
#define rf_plli_dacb_reg_plli_dac10_reg_shift 4
#define rf_plli_dacb_reg_plli_dac10_reg_mask ((1<<4)-1)
#define rf_plli_dacb_reg_plli_dac9_reg_shift 0
#define rf_plli_dacb_reg_plli_dac9_reg_mask ((1<<4)-1)

//#define rfc_plli_ctrl_reg 0x058
#define rfc_plli_ctrl_reg_plli_en_ldovco_bit (1<<12)
#define rfc_plli_ctrl_reg_plli_en_ldopll_bit (1<<11)
#define rfc_plli_ctrl_reg_plli_en_bias_bit (1<<10)
#define rfc_plli_ctrl_reg_plli_en_pll_bit (1<<9)
#define rfc_plli_ctrl_reg_plli_en_ckdig_125m_bit (1<<8)
#define rfc_plli_ctrl_reg_xo50m_en_bit (1<<7)
#define rfc_plli_ctrl_reg_xo50m_mode_bit (1<<6)
#define rfc_plli_ctrl_reg_xo50m_en_ckdig_bit (1<<5)
#define rfc_plli_ctrl_reg_xo50m_en_ckpll_bit (1<<4)
#define rfc_plli_ctrl_reg_xo50m_en_refclk_out_bit (1<<3)
#define rfc_plli_ctrl_reg_xo50m_en_ckbist_bit (1<<2)
#define rfc_plli_ctrl_reg_plli_en_ckplln_bit (1<<1)
#define rfc_plli_ctrl_reg_plli_en_ckadc_bit (1<<0)

//#define rf_plli_rega_reg 0x059
#define rf_plli_rega_reg_plli_reg4_shift 24
#define rf_plli_rega_reg_plli_reg4_mask ((1<<8)-1)
#define rf_plli_rega_reg_plli_reg3_shift 16
#define rf_plli_rega_reg_plli_reg3_mask ((1<<8)-1)
#define rf_plli_rega_reg_plli_reg2_shift 8
#define rf_plli_rega_reg_plli_reg2_mask ((1<<8)-1)
#define rf_plli_rega_reg_plli_reg1_shift 0
#define rf_plli_rega_reg_plli_reg1_mask ((1<<8)-1)

//#define rf_plli_regb_reg 0x05a
#define rf_plli_regb_reg_plli_reg8_shift 24
#define rf_plli_regb_reg_plli_reg8_mask ((1<<8)-1)
#define rf_plli_regb_reg_plli_reg7_shift 16
#define rf_plli_regb_reg_plli_reg7_mask ((1<<8)-1)
#define rf_plli_regb_reg_plli_reg6_shift 8
#define rf_plli_regb_reg_plli_reg6_mask ((1<<8)-1)
#define rf_plli_regb_reg_plli_reg5_shift 0
#define rf_plli_regb_reg_plli_reg5_mask ((1<<8)-1)

//#define rf_plli_regc_reg 0x05b
#define rf_plli_regc_reg_plli_reg10_shift 8
#define rf_plli_regc_reg_plli_reg10_mask ((1<<8)-1)
#define rf_plli_regc_reg_plli_reg9_shift 0
#define rf_plli_regc_reg_plli_reg9_mask ((1<<8)-1)

//#define rf_plli_regd_reg 0x05c
#define rf_plli_regd_reg_plli_d1t_bit (1<<4)
#define rf_plli_regd_reg_plli_d2t_bit (1<<3)
#define rf_plli_regd_reg_plli_lock_status_bit (1<<2)
#define rf_plli_regd_reg_plli_ld_hi_bit (1<<1)
#define rf_plli_regd_reg_plli_ld_lo_bit (1<<0)

//#define rf_plln_rega_reg 0x061
#define rf_plln_rega_reg_plln_reg4_shift 24
#define rf_plln_rega_reg_plln_reg4_mask ((1<<8)-1)
#define rf_plln_rega_reg_plln_reg3_shift 16
#define rf_plln_rega_reg_plln_reg3_mask ((1<<8)-1)
#define rf_plln_rega_reg_plln_reg2_shift 8
#define rf_plln_rega_reg_plln_reg2_mask ((1<<8)-1)
#define rf_plln_rega_reg_plln_reg1_shift 0
#define rf_plln_rega_reg_plln_reg1_mask ((1<<8)-1)

//#define rf_plln_regb_reg 0x062
#define rf_plln_regb_reg_plln_reg8_shift 24
#define rf_plln_regb_reg_plln_reg8_mask ((1<<8)-1)
#define rf_plln_regb_reg_plln_reg7_shift 16
#define rf_plln_regb_reg_plln_reg7_mask ((1<<8)-1)
#define rf_plln_regb_reg_plln_reg6_shift 8
#define rf_plln_regb_reg_plln_reg6_mask ((1<<8)-1)
#define rf_plln_regb_reg_plln_reg5_shift 0
#define rf_plln_regb_reg_plln_reg5_mask ((1<<8)-1)

//#define rf_plln_regc_reg 0x063
#define rf_plln_regc_reg_plln_reg12_shift 24
#define rf_plln_regc_reg_plln_reg12_mask ((1<<8)-1)
#define rf_plln_regc_reg_plln_reg11_shift 16
#define rf_plln_regc_reg_plln_reg11_mask ((1<<8)-1)
#define rf_plln_regc_reg_plln_reg10_shift 8
#define rf_plln_regc_reg_plln_reg10_mask ((1<<8)-1)
#define rf_plln_regc_reg_plln_reg9_shift 0
#define rf_plln_regc_reg_plln_reg9_mask ((1<<8)-1)

//#define rf_plln_regd_reg 0x064
#define rf_plln_regd_reg_plln_reg13_shift 0
#define rf_plln_regd_reg_plln_reg13_mask ((1<<8)-1)

//#define rf_plln_rege_reg 0x065
#define rf_plln_rege_reg_plln_d1t_bit (1<<4)
#define rf_plln_rege_reg_plln_d2t_bit (1<<3)
#define rf_plln_rege_reg_plln_lock_status_bit (1<<2)
#define rf_plln_rege_reg_plln_ld_hi_bit (1<<1)
#define rf_plln_rege_reg_plln_ld_lo_bit (1<<0)

//#define rf_plln_ldo_cfg_reg 0x066
#define rf_plln_ldo_cfg_reg_plln_bias_reg1_shift 8
#define rf_plln_ldo_cfg_reg_plln_bias_reg1_mask ((1<<4)-1)
#define rf_plln_ldo_cfg_reg_plln_ldo_reg1_shift 0
#define rf_plln_ldo_cfg_reg_plln_ldo_reg1_mask ((1<<8)-1)

//#define rf_plln_daca_reg 0x067
#define rf_plln_daca_reg_plln_dac8_reg_shift 28
#define rf_plln_daca_reg_plln_dac8_reg_mask ((1<<4)-1)
#define rf_plln_daca_reg_plln_dac7_reg_shift 24
#define rf_plln_daca_reg_plln_dac7_reg_mask ((1<<4)-1)
#define rf_plln_daca_reg_plln_dac6_reg_shift 20
#define rf_plln_daca_reg_plln_dac6_reg_mask ((1<<4)-1)
#define rf_plln_daca_reg_plln_dac5_reg_shift 16
#define rf_plln_daca_reg_plln_dac5_reg_mask ((1<<4)-1)
#define rf_plln_daca_reg_plln_dac4_reg_shift 12
#define rf_plln_daca_reg_plln_dac4_reg_mask ((1<<4)-1)
#define rf_plln_daca_reg_plln_dac3_reg_shift 8
#define rf_plln_daca_reg_plln_dac3_reg_mask ((1<<4)-1)
#define rf_plln_daca_reg_plln_dac2_reg_shift 4
#define rf_plln_daca_reg_plln_dac2_reg_mask ((1<<4)-1)
#define rf_plln_daca_reg_plln_dac1_reg_shift 0
#define rf_plln_daca_reg_plln_dac1_reg_mask ((1<<4)-1)

//#define rf_plln_dacb_reg 0x068
#define rf_plln_dacb_reg_plln_dac12_reg_shift 12
#define rf_plln_dacb_reg_plln_dac12_reg_mask ((1<<4)-1)
#define rf_plln_dacb_reg_plln_dac11_reg_shift 8
#define rf_plln_dacb_reg_plln_dac11_reg_mask ((1<<4)-1)
#define rf_plln_dacb_reg_plln_dac10_reg_shift 4
#define rf_plln_dacb_reg_plln_dac10_reg_mask ((1<<4)-1)
#define rf_plln_dacb_reg_plln_dac9_reg_shift 0
#define rf_plln_dacb_reg_plln_dac9_reg_mask ((1<<4)-1)

//#define rf_plln_ctrl_reg 0x069
#define rf_plln_ctrl_reg_plln_en_ldovco_bit (1<<2)
#define rf_plln_ctrl_reg_plln_en_ldopll_bit (1<<1)
#define rf_plln_ctrl_reg_plln_en_bias_bit (1<<0)

//#define rfc_ldo_bg_reg_reg 0x06e
#define rfc_ldo_bg_reg_reg_ldo_bg_reg_shift 0
#define rfc_ldo_bg_reg_reg_ldo_bg_reg_mask ((1<<16)-1)

//#define rf_ldo18bb_regb_reg 0x06f
#define rf_ldo18bb_regb_reg_ldo18bb_reg1_shift 3
#define rf_ldo18bb_regb_reg_ldo18bb_reg1_mask ((1<<3)-1)
#define rf_ldo18bb_regb_reg_ldo18bb_reg0_shift 0
#define rf_ldo18bb_regb_reg_ldo18bb_reg0_mask ((1<<3)-1)

//#define rfc_ldo12n_rega_reg 0x070
#define rfc_ldo12n_rega_reg_ldo12_lp_vcfg_shift 10
#define rfc_ldo12n_rega_reg_ldo12_lp_vcfg_mask ((1<<3)-1)
#define rfc_ldo12n_rega_reg_ldo12_hp_vcfg_shift 8
#define rfc_ldo12n_rega_reg_ldo12_hp_vcfg_mask ((1<<2)-1)
#define rfc_ldo12n_rega_reg_ldo12_reg_shift 0
#define rfc_ldo12n_rega_reg_ldo12_reg_mask ((1<<8)-1)

//#define rf_buf20g_db_reg 0x081
#define rf_buf20g_db_reg_lo_reg_shift 2
#define rf_buf20g_db_reg_lo_reg_mask ((1<<2)-1)
#define rf_buf20g_db_reg_buf20g_en_bit (1<<1)
#define rf_buf20g_db_reg_dbl_en_bit (1<<0)

//#define rf_buf77g_ctrl_reg 0x082
#define rf_buf77g_ctrl_reg_buff77g_en_bit (1<<4)
#define rf_buf77g_ctrl_reg_buff77g_en_tx0_bit (1<<3)
#define rf_buf77g_ctrl_reg_buff77g_en_tx1_bit (1<<2)
#define rf_buf77g_ctrl_reg_buff77g_en_rx0_bit (1<<1)
#define rf_buf77g_ctrl_reg_buff77g_en_rx1_bit (1<<0)

//#define rfc_tx_pa_reg 0x083
#define rfc_tx_pa_reg_rf_atb_sel_shift 8
#define rfc_tx_pa_reg_rf_atb_sel_mask ((1<<3)-1)
#define rfc_tx_pa_reg_rf_atb_en_shift 2
#define rfc_tx_pa_reg_rf_atb_en_mask ((1<<6)-1)
#define rfc_tx_pa_reg_pa1_en_bit (1<<1)
#define rfc_tx_pa_reg_pa0_en_bit (1<<0)

//#define rfc_phase_shift_reg 0x084
#define rfc_phase_shift_reg_ps_auto_en_bit (1<<20)
#define rfc_phase_shift_reg_ps_ip_shift 15
#define rfc_phase_shift_reg_ps_ip_mask ((1<<5)-1)
#define rfc_phase_shift_reg_ps_in_shift 10
#define rfc_phase_shift_reg_ps_in_mask ((1<<5)-1)
#define rfc_phase_shift_reg_ps_qp_shift 5
#define rfc_phase_shift_reg_ps_qp_mask ((1<<5)-1)
#define rfc_phase_shift_reg_ps_qn_shift 0
#define rfc_phase_shift_reg_ps_qn_mask ((1<<5)-1)

//#define rfc_rx_lna_reg 0x085
#define rfc_rx_lna_reg_mixer_reg_shift 4
#define rfc_rx_lna_reg_mixer_reg_mask ((1<<2)-1)
#define rfc_rx_lna_reg_lna_reg_shift 2
#define rfc_rx_lna_reg_lna_reg_mask ((1<<2)-1)
#define rfc_rx_lna_reg_lna1_en_bit (1<<1)
#define rfc_rx_lna_reg_lna0_en_bit (1<<0)

//#define rfc_tia0_cfg_reg 0x086
#define rfc_tia0_cfg_reg_tia0_en_bit (1<<12)
#define rfc_tia0_cfg_reg_tia0_q_gain_shift 10
#define rfc_tia0_cfg_reg_tia0_q_gain_mask ((1<<2)-1)
#define rfc_tia0_cfg_reg_tia0_i_gain_shift 8
#define rfc_tia0_cfg_reg_tia0_i_gain_mask ((1<<2)-1)
#define rfc_tia0_cfg_reg_tia0_reg_shift 0
#define rfc_tia0_cfg_reg_tia0_reg_mask ((1<<8)-1)

//#define rfc_tia1_cfg_reg 0x087
#define rfc_tia1_cfg_reg_tia1_en_bit (1<<12)
#define rfc_tia1_cfg_reg_tia1_q_gain_shift 10
#define rfc_tia1_cfg_reg_tia1_q_gain_mask ((1<<2)-1)
#define rfc_tia1_cfg_reg_tia1_i_gain_shift 8
#define rfc_tia1_cfg_reg_tia1_i_gain_mask ((1<<2)-1)
#define rfc_tia1_cfg_reg_tia1_reg_shift 0
#define rfc_tia1_cfg_reg_tia1_reg_mask ((1<<8)-1)

//#define rfc_vga0_reg 0x088
#define rfc_vga0_reg_pga0_en_bit (1<<26)
#define rfc_vga0_reg_pga0_q_gain_shift 21
#define rfc_vga0_reg_pga0_q_gain_mask ((1<<5)-1)
#define rfc_vga0_reg_pga0_i_gain_shift 16
#define rfc_vga0_reg_pga0_i_gain_mask ((1<<5)-1)
#define rfc_vga0_reg_pga0_reg2_shift 8
#define rfc_vga0_reg_pga0_reg2_mask ((1<<8)-1)
#define rfc_vga0_reg_pga0_reg1_shift 0
#define rfc_vga0_reg_pga0_reg1_mask ((1<<8)-1)

//#define rfc_vga1_reg 0x089
#define rfc_vga1_reg_pga1_en_bit (1<<26)
#define rfc_vga1_reg_pga1_q_gain_shift 21
#define rfc_vga1_reg_pga1_q_gain_mask ((1<<5)-1)
#define rfc_vga1_reg_pga1_i_gain_shift 16
#define rfc_vga1_reg_pga1_i_gain_mask ((1<<5)-1)
#define rfc_vga1_reg_pga1_reg2_shift 8
#define rfc_vga1_reg_pga1_reg2_mask ((1<<8)-1)
#define rfc_vga1_reg_pga1_reg1_shift 0
#define rfc_vga1_reg_pga1_reg1_mask ((1<<8)-1)

//#define rf_bist_cfg_reg 0x09a
#define rf_bist_cfg_reg_bist_reg3_shift 24
#define rf_bist_cfg_reg_bist_reg3_mask ((1<<8)-1)
#define rf_bist_cfg_reg_bist_reg2_shift 16
#define rf_bist_cfg_reg_bist_reg2_mask ((1<<8)-1)
#define rf_bist_cfg_reg_bist_reg1_shift 8
#define rf_bist_cfg_reg_bist_reg1_mask ((1<<8)-1)
#define rf_bist_cfg_reg_bist_reg0_shift 0
#define rf_bist_cfg_reg_bist_reg0_mask ((1<<8)-1)

//#define rf_bist_load 0x09b

//#define rf_bist_data_sync 0x09c

//#define rf_atb_cfg_reg 0x09d
#define rf_atb_cfg_reg_atb_cfg2_shift 4
#define rf_atb_cfg_reg_atb_cfg2_mask ((1<<4)-1)
#define rf_atb_cfg_reg_atb_cfg1_shift 0
#define rf_atb_cfg_reg_atb_cfg1_mask ((1<<4)-1)

//#define rf_spare_reg 0x09e
#define rf_spare_reg_ar_spare_reg2_shift 4
#define rf_spare_reg_ar_spare_reg2_mask ((1<<4)-1)
#define rf_spare_reg_ar_spare_reg1_shift 0
#define rf_spare_reg_ar_spare_reg1_mask ((1<<4)-1)

//#define lut_reg0_reg 0x100
#define lut_reg0_reg_lut0_high_shift 0
#define lut_reg0_reg_lut0_high_mask ((1<<8)-1)

//#define lut_reg1_reg 0x101
#define lut_reg1_reg_lut0_mid_shift 0
#define lut_reg1_reg_lut0_mid_mask ((1<<8)-1)

//#define lut_reg2_reg 0x102
#define lut_reg2_reg_lut1_high_shift 0
#define lut_reg2_reg_lut1_high_mask ((1<<8)-1)

//#define lut_reg3_reg 0x103
#define lut_reg3_reg_lut1_mid_shift 0
#define lut_reg3_reg_lut1_mid_mask ((1<<8)-1)

//#define lut_reg4_reg 0x104
#define lut_reg4_reg_lut2_high_shift 0
#define lut_reg4_reg_lut2_high_mask ((1<<8)-1)

//#define lut_reg5_reg 0x105
#define lut_reg5_reg_lut2_mid_shift 0
#define lut_reg5_reg_lut2_mid_mask ((1<<8)-1)

//#define lut_reg6_reg 0x106
#define lut_reg6_reg_lut3_high_shift 0
#define lut_reg6_reg_lut3_high_mask ((1<<8)-1)

//#define lut_reg7_reg 0x107
#define lut_reg7_reg_lut3_mid_shift 0
#define lut_reg7_reg_lut3_mid_mask ((1<<8)-1)

//#define lut_reg8_reg 0x108
#define lut_reg8_reg_lut4_high_shift 0
#define lut_reg8_reg_lut4_high_mask ((1<<8)-1)

//#define lut_reg9_reg 0x109
#define lut_reg9_reg_lut4_mid_shift 0
#define lut_reg9_reg_lut4_mid_mask ((1<<8)-1)

//#define lut_reg10_reg 0x10a
#define lut_reg10_reg_lut5_high_shift 0
#define lut_reg10_reg_lut5_high_mask ((1<<8)-1)

//#define lut_reg11_reg 0x10b
#define lut_reg11_reg_lut5_mid_shift 0
#define lut_reg11_reg_lut5_mid_mask ((1<<8)-1)

//#define lut_reg12_reg 0x10c
#define lut_reg12_reg_lut6_high_shift 0
#define lut_reg12_reg_lut6_high_mask ((1<<8)-1)

//#define lut_reg13_reg 0x10d
#define lut_reg13_reg_lut6_mid_shift 0
#define lut_reg13_reg_lut6_mid_mask ((1<<8)-1)

//#define lut_reg14_reg 0x10e
#define lut_reg14_reg_lut7_high_shift 0
#define lut_reg14_reg_lut7_high_mask ((1<<8)-1)

//#define lut_reg15_reg 0x10f
#define lut_reg15_reg_lut7_mid_shift 0
#define lut_reg15_reg_lut7_mid_mask ((1<<8)-1)

//#define lut_reg16_reg 0x110
#define lut_reg16_reg_lut8_high_shift 0
#define lut_reg16_reg_lut8_high_mask ((1<<8)-1)

//#define lut_reg17_reg 0x111
#define lut_reg17_reg_lut8_mid_shift 0
#define lut_reg17_reg_lut8_mid_mask ((1<<8)-1)

//#define lut_reg18_reg 0x112
#define lut_reg18_reg_lut9_high_shift 0
#define lut_reg18_reg_lut9_high_mask ((1<<8)-1)

//#define lut_reg19_reg 0x113
#define lut_reg19_reg_lut9_mid_shift 0
#define lut_reg19_reg_lut9_mid_mask ((1<<8)-1)

//#define lut_reg20_reg 0x114
#define lut_reg20_reg_lut10_high_shift 0
#define lut_reg20_reg_lut10_high_mask ((1<<8)-1)

//#define lut_reg21_reg 0x115
#define lut_reg21_reg_lut10_mid_shift 0
#define lut_reg21_reg_lut10_mid_mask ((1<<8)-1)

//#define lut_reg22_reg 0x116
#define lut_reg22_reg_lut11_high_shift 0
#define lut_reg22_reg_lut11_high_mask ((1<<8)-1)

//#define lut_reg23_reg 0x117
#define lut_reg23_reg_lut11_mid_shift 0
#define lut_reg23_reg_lut11_mid_mask ((1<<8)-1)

//#define lut_reg24_reg 0x118
#define lut_reg24_reg_lut12_high_shift 0
#define lut_reg24_reg_lut12_high_mask ((1<<8)-1)

//#define lut_reg25_reg 0x119
#define lut_reg25_reg_lut12_mid_shift 0
#define lut_reg25_reg_lut12_mid_mask ((1<<8)-1)

//#define lut_reg26_reg 0x11a
#define lut_reg26_reg_lut13_high_shift 0
#define lut_reg26_reg_lut13_high_mask ((1<<8)-1)

//#define lut_reg27_reg 0x11b
#define lut_reg27_reg_lut13_mid_shift 0
#define lut_reg27_reg_lut13_mid_mask ((1<<8)-1)

//#define lut_reg28_reg 0x11c
#define lut_reg28_reg_lut14_high_shift 0
#define lut_reg28_reg_lut14_high_mask ((1<<8)-1)

//#define lut_reg29_reg 0x11d
#define lut_reg29_reg_lut14_mid_shift 0
#define lut_reg29_reg_lut14_mid_mask ((1<<8)-1)

//#define lut_reg30_reg 0x11e
#define lut_reg30_reg_lut15_high_shift 0
#define lut_reg30_reg_lut15_high_mask ((1<<8)-1)

//#define lut_reg31_reg 0x11f
#define lut_reg31_reg_lut15_mid_shift 0
#define lut_reg31_reg_lut15_mid_mask ((1<<8)-1)

//#define lut_reg32_reg 0x120
#define lut_reg32_reg_lut16_high_shift 0
#define lut_reg32_reg_lut16_high_mask ((1<<8)-1)

//#define lut_reg33_reg 0x121
#define lut_reg33_reg_lut16_mid_shift 0
#define lut_reg33_reg_lut16_mid_mask ((1<<8)-1)

//#define lut_reg34_reg 0x122
#define lut_reg34_reg_lut17_high_shift 0
#define lut_reg34_reg_lut17_high_mask ((1<<8)-1)

//#define lut_reg35_reg 0x123
#define lut_reg35_reg_lut17_mid_shift 0
#define lut_reg35_reg_lut17_mid_mask ((1<<8)-1)

//#define lut_reg36_reg 0x124
#define lut_reg36_reg_lut18_high_shift 0
#define lut_reg36_reg_lut18_high_mask ((1<<8)-1)

//#define lut_reg37_reg 0x125
#define lut_reg37_reg_lut18_mid_shift 0
#define lut_reg37_reg_lut18_mid_mask ((1<<8)-1)

//#define lut_reg38_reg 0x126
#define lut_reg38_reg_lut19_high_shift 0
#define lut_reg38_reg_lut19_high_mask ((1<<8)-1)

//#define lut_reg39_reg 0x127
#define lut_reg39_reg_lut19_mid_shift 0
#define lut_reg39_reg_lut19_mid_mask ((1<<8)-1)

//#define lut_reg40_reg 0x128
#define lut_reg40_reg_lut20_high_shift 0
#define lut_reg40_reg_lut20_high_mask ((1<<8)-1)

//#define lut_reg41_reg 0x129
#define lut_reg41_reg_lut20_mid_shift 0
#define lut_reg41_reg_lut20_mid_mask ((1<<8)-1)

//#define lut_reg42_reg 0x12a
#define lut_reg42_reg_lut21_high_shift 0
#define lut_reg42_reg_lut21_high_mask ((1<<8)-1)

//#define lut_reg43_reg 0x12b
#define lut_reg43_reg_lut21_mid_shift 0
#define lut_reg43_reg_lut21_mid_mask ((1<<8)-1)

//#define lut_reg44_reg 0x12c
#define lut_reg44_reg_lut22_high_shift 0
#define lut_reg44_reg_lut22_high_mask ((1<<8)-1)

//#define lut_reg45_reg 0x12d
#define lut_reg45_reg_lut22_mid_shift 0
#define lut_reg45_reg_lut22_mid_mask ((1<<8)-1)

//#define lut_reg46_reg 0x12e
#define lut_reg46_reg_lut23_high_shift 0
#define lut_reg46_reg_lut23_high_mask ((1<<8)-1)

//#define lut_reg47_reg 0x12f
#define lut_reg47_reg_lut23_mid_shift 0
#define lut_reg47_reg_lut23_mid_mask ((1<<8)-1)

//#define lut_reg48_reg 0x130
#define lut_reg48_reg_lut24_high_shift 0
#define lut_reg48_reg_lut24_high_mask ((1<<8)-1)

//#define lut_reg49_reg 0x131
#define lut_reg49_reg_lut24_mid_shift 0
#define lut_reg49_reg_lut24_mid_mask ((1<<8)-1)

//#define lut_reg50_reg 0x132
#define lut_reg50_reg_lut25_high_shift 0
#define lut_reg50_reg_lut25_high_mask ((1<<8)-1)

//#define lut_reg51_reg 0x133
#define lut_reg51_reg_lut25_mid_shift 0
#define lut_reg51_reg_lut25_mid_mask ((1<<8)-1)

//#define lut_reg52_reg 0x134
#define lut_reg52_reg_lut26_high_shift 0
#define lut_reg52_reg_lut26_high_mask ((1<<8)-1)

//#define lut_reg53_reg 0x135
#define lut_reg53_reg_lut26_mid_shift 0
#define lut_reg53_reg_lut26_mid_mask ((1<<8)-1)

//#define lut_reg54_reg 0x136
#define lut_reg54_reg_lut27_high_shift 0
#define lut_reg54_reg_lut27_high_mask ((1<<8)-1)

//#define lut_reg55_reg 0x137
#define lut_reg55_reg_lut27_mid_shift 0
#define lut_reg55_reg_lut27_mid_mask ((1<<8)-1)

//#define lut_reg56_reg 0x138
#define lut_reg56_reg_lut28_high_shift 0
#define lut_reg56_reg_lut28_high_mask ((1<<8)-1)

//#define lut_reg57_reg 0x139
#define lut_reg57_reg_lut28_mid_shift 0
#define lut_reg57_reg_lut28_mid_mask ((1<<8)-1)

//#define lut_reg58_reg 0x13a
#define lut_reg58_reg_lut29_high_shift 0
#define lut_reg58_reg_lut29_high_mask ((1<<8)-1)

//#define lut_reg59_reg 0x13b
#define lut_reg59_reg_lut29_mid_shift 0
#define lut_reg59_reg_lut29_mid_mask ((1<<8)-1)

//#define lut_reg60_reg 0x13c
#define lut_reg60_reg_lut30_high_shift 0
#define lut_reg60_reg_lut30_high_mask ((1<<8)-1)

//#define lut_reg61_reg 0x13d
#define lut_reg61_reg_lut30_mid_shift 0
#define lut_reg61_reg_lut30_mid_mask ((1<<8)-1)

//#define lut_reg62_reg 0x13e
#define lut_reg62_reg_lut31_high_shift 0
#define lut_reg62_reg_lut31_high_mask ((1<<8)-1)

//#define lut_reg63_reg 0x13f
#define lut_reg63_reg_lut31_mid_shift 0
#define lut_reg63_reg_lut31_mid_mask ((1<<8)-1)

//#define lut_reg64_reg 0x140
#define lut_reg64_reg_lut32_high_shift 0
#define lut_reg64_reg_lut32_high_mask ((1<<8)-1)

//#define lut_reg65_reg 0x141
#define lut_reg65_reg_lut32_mid_shift 0
#define lut_reg65_reg_lut32_mid_mask ((1<<8)-1)

//#define lut_reg66_reg 0x142
#define lut_reg66_reg_lut33_high_shift 0
#define lut_reg66_reg_lut33_high_mask ((1<<8)-1)

//#define lut_reg67_reg 0x143
#define lut_reg67_reg_lut33_mid_shift 0
#define lut_reg67_reg_lut33_mid_mask ((1<<8)-1)

//#define lut_reg68_reg 0x144
#define lut_reg68_reg_lut34_high_shift 0
#define lut_reg68_reg_lut34_high_mask ((1<<8)-1)

//#define lut_reg69_reg 0x145
#define lut_reg69_reg_lut34_mid_shift 0
#define lut_reg69_reg_lut34_mid_mask ((1<<8)-1)

//#define lut_reg70_reg 0x146
#define lut_reg70_reg_lut35_high_shift 0
#define lut_reg70_reg_lut35_high_mask ((1<<8)-1)

//#define lut_reg71_reg 0x147
#define lut_reg71_reg_lut35_mid_shift 0
#define lut_reg71_reg_lut35_mid_mask ((1<<8)-1)

//#define lut_reg72_reg 0x148
#define lut_reg72_reg_lut36_high_shift 0
#define lut_reg72_reg_lut36_high_mask ((1<<8)-1)

//#define lut_reg73_reg 0x149
#define lut_reg73_reg_lut36_mid_shift 0
#define lut_reg73_reg_lut36_mid_mask ((1<<8)-1)

//#define lut_reg74_reg 0x14a
#define lut_reg74_reg_lut37_high_shift 0
#define lut_reg74_reg_lut37_high_mask ((1<<8)-1)

//#define lut_reg75_reg 0x14b
#define lut_reg75_reg_lut37_mid_shift 0
#define lut_reg75_reg_lut37_mid_mask ((1<<8)-1)

//#define lut_reg76_reg 0x14c
#define lut_reg76_reg_lut38_high_shift 0
#define lut_reg76_reg_lut38_high_mask ((1<<8)-1)

//#define lut_reg77_reg 0x14d
#define lut_reg77_reg_lut38_mid_shift 0
#define lut_reg77_reg_lut38_mid_mask ((1<<8)-1)

//#define lut_reg78_reg 0x14e
#define lut_reg78_reg_lut39_high_shift 0
#define lut_reg78_reg_lut39_high_mask ((1<<8)-1)

//#define lut_reg79_reg 0x14f
#define lut_reg79_reg_lut39_mid_shift 0
#define lut_reg79_reg_lut39_mid_mask ((1<<8)-1)

//#define lut_reg80_reg 0x150
#define lut_reg80_reg_lut40_high_shift 0
#define lut_reg80_reg_lut40_high_mask ((1<<8)-1)

//#define lut_reg81_reg 0x151
#define lut_reg81_reg_lut40_mid_shift 0
#define lut_reg81_reg_lut40_mid_mask ((1<<8)-1)

//#define lut_reg82_reg 0x152
#define lut_reg82_reg_lut41_high_shift 0
#define lut_reg82_reg_lut41_high_mask ((1<<8)-1)

//#define lut_reg83_reg 0x153
#define lut_reg83_reg_lut41_mid_shift 0
#define lut_reg83_reg_lut41_mid_mask ((1<<8)-1)

//#define lut_reg84_reg 0x154
#define lut_reg84_reg_lut42_high_shift 0
#define lut_reg84_reg_lut42_high_mask ((1<<8)-1)

//#define lut_reg85_reg 0x155
#define lut_reg85_reg_lut42_mid_shift 0
#define lut_reg85_reg_lut42_mid_mask ((1<<8)-1)

//#define lut_reg86_reg 0x156
#define lut_reg86_reg_lut43_high_shift 0
#define lut_reg86_reg_lut43_high_mask ((1<<8)-1)

//#define lut_reg87_reg 0x157
#define lut_reg87_reg_lut43_mid_shift 0
#define lut_reg87_reg_lut43_mid_mask ((1<<8)-1)

//#define lut_reg88_reg 0x158
#define lut_reg88_reg_lut44_high_shift 0
#define lut_reg88_reg_lut44_high_mask ((1<<8)-1)

//#define lut_reg89_reg 0x159
#define lut_reg89_reg_lut44_mid_shift 0
#define lut_reg89_reg_lut44_mid_mask ((1<<8)-1)

//#define lut_reg90_reg 0x15a
#define lut_reg90_reg_lut45_high_shift 0
#define lut_reg90_reg_lut45_high_mask ((1<<8)-1)

//#define lut_reg91_reg 0x15b
#define lut_reg91_reg_lut45_mid_shift 0
#define lut_reg91_reg_lut45_mid_mask ((1<<8)-1)

//#define lut_reg92_reg 0x15c
#define lut_reg92_reg_lut46_high_shift 0
#define lut_reg92_reg_lut46_high_mask ((1<<8)-1)

//#define lut_reg93_reg 0x15d
#define lut_reg93_reg_lut46_mid_shift 0
#define lut_reg93_reg_lut46_mid_mask ((1<<8)-1)

//#define lut_reg94_reg 0x15e
#define lut_reg94_reg_lut47_high_shift 0
#define lut_reg94_reg_lut47_high_mask ((1<<8)-1)

//#define lut_reg95_reg 0x15f
#define lut_reg95_reg_lut47_mid_shift 0
#define lut_reg95_reg_lut47_mid_mask ((1<<8)-1)

//#define lut_reg96_reg 0x160
#define lut_reg96_reg_lut48_high_shift 0
#define lut_reg96_reg_lut48_high_mask ((1<<8)-1)

//#define lut_reg97_reg 0x161
#define lut_reg97_reg_lut48_mid_shift 0
#define lut_reg97_reg_lut48_mid_mask ((1<<8)-1)

//#define lut_reg98_reg 0x162
#define lut_reg98_reg_lut49_high_shift 0
#define lut_reg98_reg_lut49_high_mask ((1<<8)-1)

//#define lut_reg99_reg 0x163
#define lut_reg99_reg_lut49_mid_shift 0
#define lut_reg99_reg_lut49_mid_mask ((1<<8)-1)

//#define lut_reg100_reg 0x164
#define lut_reg100_reg_lut50_high_shift 0
#define lut_reg100_reg_lut50_high_mask ((1<<8)-1)

//#define lut_reg101_reg 0x165
#define lut_reg101_reg_lut50_mid_shift 0
#define lut_reg101_reg_lut50_mid_mask ((1<<8)-1)

//#define lut_reg102_reg 0x166
#define lut_reg102_reg_lut51_high_shift 0
#define lut_reg102_reg_lut51_high_mask ((1<<8)-1)

//#define lut_reg103_reg 0x167
#define lut_reg103_reg_lut51_mid_shift 0
#define lut_reg103_reg_lut51_mid_mask ((1<<8)-1)

//#define lut_reg104_reg 0x168
#define lut_reg104_reg_lut52_high_shift 0
#define lut_reg104_reg_lut52_high_mask ((1<<8)-1)

//#define lut_reg105_reg 0x169
#define lut_reg105_reg_lut52_mid_shift 0
#define lut_reg105_reg_lut52_mid_mask ((1<<8)-1)

//#define lut_reg106_reg 0x16a
#define lut_reg106_reg_lut53_high_shift 0
#define lut_reg106_reg_lut53_high_mask ((1<<8)-1)

//#define lut_reg107_reg 0x16b
#define lut_reg107_reg_lut53_mid_shift 0
#define lut_reg107_reg_lut53_mid_mask ((1<<8)-1)

//#define lut_reg108_reg 0x16c
#define lut_reg108_reg_lut54_high_shift 0
#define lut_reg108_reg_lut54_high_mask ((1<<8)-1)

//#define lut_reg109_reg 0x16d
#define lut_reg109_reg_lut54_mid_shift 0
#define lut_reg109_reg_lut54_mid_mask ((1<<8)-1)

//#define lut_reg110_reg 0x16e
#define lut_reg110_reg_lut55_high_shift 0
#define lut_reg110_reg_lut55_high_mask ((1<<8)-1)

//#define lut_reg111_reg 0x16f
#define lut_reg111_reg_lut55_mid_shift 0
#define lut_reg111_reg_lut55_mid_mask ((1<<8)-1)

//#define lut_reg112_reg 0x170
#define lut_reg112_reg_lut56_high_shift 0
#define lut_reg112_reg_lut56_high_mask ((1<<8)-1)

//#define lut_reg113_reg 0x171
#define lut_reg113_reg_lut56_mid_shift 0
#define lut_reg113_reg_lut56_mid_mask ((1<<8)-1)

//#define lut_reg114_reg 0x172
#define lut_reg114_reg_lut57_high_shift 0
#define lut_reg114_reg_lut57_high_mask ((1<<8)-1)

//#define lut_reg115_reg 0x173
#define lut_reg115_reg_lut57_mid_shift 0
#define lut_reg115_reg_lut57_mid_mask ((1<<8)-1)

//#define lut_reg116_reg 0x174
#define lut_reg116_reg_lut58_high_shift 0
#define lut_reg116_reg_lut58_high_mask ((1<<8)-1)

//#define lut_reg117_reg 0x175
#define lut_reg117_reg_lut58_mid_shift 0
#define lut_reg117_reg_lut58_mid_mask ((1<<8)-1)

//#define lut_reg118_reg 0x176
#define lut_reg118_reg_lut59_high_shift 0
#define lut_reg118_reg_lut59_high_mask ((1<<8)-1)

//#define lut_reg119_reg 0x177
#define lut_reg119_reg_lut59_mid_shift 0
#define lut_reg119_reg_lut59_mid_mask ((1<<8)-1)

//#define lut_reg120_reg 0x178
#define lut_reg120_reg_lut60_high_shift 0
#define lut_reg120_reg_lut60_high_mask ((1<<8)-1)

//#define lut_reg121_reg 0x179
#define lut_reg121_reg_lut60_mid_shift 0
#define lut_reg121_reg_lut60_mid_mask ((1<<8)-1)

//#define lut_reg122_reg 0x17a
#define lut_reg122_reg_lut61_high_shift 0
#define lut_reg122_reg_lut61_high_mask ((1<<8)-1)

//#define lut_reg123_reg 0x17b
#define lut_reg123_reg_lut61_mid_shift 0
#define lut_reg123_reg_lut61_mid_mask ((1<<8)-1)

//#define lut_reg124_reg 0x17c
#define lut_reg124_reg_lut62_high_shift 0
#define lut_reg124_reg_lut62_high_mask ((1<<8)-1)

//#define lut_reg125_reg 0x17d
#define lut_reg125_reg_lut62_mid_shift 0
#define lut_reg125_reg_lut62_mid_mask ((1<<8)-1)

//#define lut_reg126_reg 0x17e
#define lut_reg126_reg_lut63_high_shift 0
#define lut_reg126_reg_lut63_high_mask ((1<<8)-1)

//#define lut_reg127_reg 0x17f
#define lut_reg127_reg_lut63_mid_shift 0
#define lut_reg127_reg_lut63_mid_mask ((1<<8)-1)

//#define lut_reg128_reg 0x180
#define lut_reg128_reg_lut0_low_shift 4
#define lut_reg128_reg_lut0_low_mask ((1<<4)-1)
#define lut_reg128_reg_lut1_low_shift 0
#define lut_reg128_reg_lut1_low_mask ((1<<4)-1)

//#define lut_reg129_reg 0x181
#define lut_reg129_reg_lut2_low_shift 4
#define lut_reg129_reg_lut2_low_mask ((1<<4)-1)
#define lut_reg129_reg_lut3_low_shift 0
#define lut_reg129_reg_lut3_low_mask ((1<<4)-1)

//#define lut_reg130_reg 0x182
#define lut_reg130_reg_lut4_low_shift 4
#define lut_reg130_reg_lut4_low_mask ((1<<4)-1)
#define lut_reg130_reg_lut5_low_shift 0
#define lut_reg130_reg_lut5_low_mask ((1<<4)-1)

//#define lut_reg131_reg 0x183
#define lut_reg131_reg_lut6_low_shift 4
#define lut_reg131_reg_lut6_low_mask ((1<<4)-1)
#define lut_reg131_reg_lut7_low_shift 0
#define lut_reg131_reg_lut7_low_mask ((1<<4)-1)

//#define lut_reg132_reg 0x184
#define lut_reg132_reg_lut8_low_shift 4
#define lut_reg132_reg_lut8_low_mask ((1<<4)-1)
#define lut_reg132_reg_lut9_low_shift 0
#define lut_reg132_reg_lut9_low_mask ((1<<4)-1)

//#define lut_reg133_reg 0x185
#define lut_reg133_reg_lut10_low_shift 4
#define lut_reg133_reg_lut10_low_mask ((1<<4)-1)
#define lut_reg133_reg_lut11_low_shift 0
#define lut_reg133_reg_lut11_low_mask ((1<<4)-1)

//#define lut_reg134_reg 0x186
#define lut_reg134_reg_lut12_low_shift 4
#define lut_reg134_reg_lut12_low_mask ((1<<4)-1)
#define lut_reg134_reg_lut13_low_shift 0
#define lut_reg134_reg_lut13_low_mask ((1<<4)-1)

//#define lut_reg135_reg 0x187
#define lut_reg135_reg_lut14_low_shift 4
#define lut_reg135_reg_lut14_low_mask ((1<<4)-1)
#define lut_reg135_reg_lut15_low_shift 0
#define lut_reg135_reg_lut15_low_mask ((1<<4)-1)

//#define lut_reg136_reg 0x188
#define lut_reg136_reg_lut16_low_shift 4
#define lut_reg136_reg_lut16_low_mask ((1<<4)-1)
#define lut_reg136_reg_lut17_low_shift 0
#define lut_reg136_reg_lut17_low_mask ((1<<4)-1)

//#define lut_reg137_reg 0x189
#define lut_reg137_reg_lut18_low_shift 4
#define lut_reg137_reg_lut18_low_mask ((1<<4)-1)
#define lut_reg137_reg_lut19_low_shift 0
#define lut_reg137_reg_lut19_low_mask ((1<<4)-1)

//#define lut_reg138_reg 0x18a
#define lut_reg138_reg_lut20_low_shift 4
#define lut_reg138_reg_lut20_low_mask ((1<<4)-1)
#define lut_reg138_reg_lut21_low_shift 0
#define lut_reg138_reg_lut21_low_mask ((1<<4)-1)

//#define lut_reg139_reg 0x18b
#define lut_reg139_reg_lut22_low_shift 4
#define lut_reg139_reg_lut22_low_mask ((1<<4)-1)
#define lut_reg139_reg_lut23_low_shift 0
#define lut_reg139_reg_lut23_low_mask ((1<<4)-1)

//#define lut_reg140_reg 0x18c
#define lut_reg140_reg_lut24_low_shift 4
#define lut_reg140_reg_lut24_low_mask ((1<<4)-1)
#define lut_reg140_reg_lut25_low_shift 0
#define lut_reg140_reg_lut25_low_mask ((1<<4)-1)

//#define lut_reg141_reg 0x18d
#define lut_reg141_reg_lut26_low_shift 4
#define lut_reg141_reg_lut26_low_mask ((1<<4)-1)
#define lut_reg141_reg_lut27_low_shift 0
#define lut_reg141_reg_lut27_low_mask ((1<<4)-1)

//#define lut_reg142_reg 0x18e
#define lut_reg142_reg_lut28_low_shift 4
#define lut_reg142_reg_lut28_low_mask ((1<<4)-1)
#define lut_reg142_reg_lut29_low_shift 0
#define lut_reg142_reg_lut29_low_mask ((1<<4)-1)

//#define lut_reg143_reg 0x18f
#define lut_reg143_reg_lut30_low_shift 4
#define lut_reg143_reg_lut30_low_mask ((1<<4)-1)
#define lut_reg143_reg_lut31_low_shift 0
#define lut_reg143_reg_lut31_low_mask ((1<<4)-1)

//#define lut_reg144_reg 0x190
#define lut_reg144_reg_lut32_low_shift 4
#define lut_reg144_reg_lut32_low_mask ((1<<4)-1)
#define lut_reg144_reg_lut33_low_shift 0
#define lut_reg144_reg_lut33_low_mask ((1<<4)-1)

//#define lut_reg145_reg 0x191
#define lut_reg145_reg_lut34_low_shift 4
#define lut_reg145_reg_lut34_low_mask ((1<<4)-1)
#define lut_reg145_reg_lut35_low_shift 0
#define lut_reg145_reg_lut35_low_mask ((1<<4)-1)

//#define lut_reg146_reg 0x192
#define lut_reg146_reg_lut36_low_shift 4
#define lut_reg146_reg_lut36_low_mask ((1<<4)-1)
#define lut_reg146_reg_lut37_low_shift 0
#define lut_reg146_reg_lut37_low_mask ((1<<4)-1)

//#define lut_reg147_reg 0x193
#define lut_reg147_reg_lut38_low_shift 4
#define lut_reg147_reg_lut38_low_mask ((1<<4)-1)
#define lut_reg147_reg_lut39_low_shift 0
#define lut_reg147_reg_lut39_low_mask ((1<<4)-1)

//#define lut_reg148_reg 0x194
#define lut_reg148_reg_lut40_low_shift 4
#define lut_reg148_reg_lut40_low_mask ((1<<4)-1)
#define lut_reg148_reg_lut41_low_shift 0
#define lut_reg148_reg_lut41_low_mask ((1<<4)-1)

//#define lut_reg149_reg 0x195
#define lut_reg149_reg_lut42_low_shift 4
#define lut_reg149_reg_lut42_low_mask ((1<<4)-1)
#define lut_reg149_reg_lut43_low_shift 0
#define lut_reg149_reg_lut43_low_mask ((1<<4)-1)

//#define lut_reg150_reg 0x196
#define lut_reg150_reg_lut44_low_shift 4
#define lut_reg150_reg_lut44_low_mask ((1<<4)-1)
#define lut_reg150_reg_lut45_low_shift 0
#define lut_reg150_reg_lut45_low_mask ((1<<4)-1)

//#define lut_reg151_reg 0x197
#define lut_reg151_reg_lut46_low_shift 4
#define lut_reg151_reg_lut46_low_mask ((1<<4)-1)
#define lut_reg151_reg_lut47_low_shift 0
#define lut_reg151_reg_lut47_low_mask ((1<<4)-1)

//#define lut_reg152_reg 0x198
#define lut_reg152_reg_lut48_low_shift 4
#define lut_reg152_reg_lut48_low_mask ((1<<4)-1)
#define lut_reg152_reg_lut49_low_shift 0
#define lut_reg152_reg_lut49_low_mask ((1<<4)-1)

//#define lut_reg153_reg 0x199
#define lut_reg153_reg_lut50_low_shift 4
#define lut_reg153_reg_lut50_low_mask ((1<<4)-1)
#define lut_reg153_reg_lut51_low_shift 0
#define lut_reg153_reg_lut51_low_mask ((1<<4)-1)

//#define lut_reg154_reg 0x19a
#define lut_reg154_reg_lut52_low_shift 4
#define lut_reg154_reg_lut52_low_mask ((1<<4)-1)
#define lut_reg154_reg_lut53_low_shift 0
#define lut_reg154_reg_lut53_low_mask ((1<<4)-1)

//#define lut_reg155_reg 0x19b
#define lut_reg155_reg_lut54_low_shift 4
#define lut_reg155_reg_lut54_low_mask ((1<<4)-1)
#define lut_reg155_reg_lut55_low_shift 0
#define lut_reg155_reg_lut55_low_mask ((1<<4)-1)

//#define lut_reg156_reg 0x19c
#define lut_reg156_reg_lut56_low_shift 4
#define lut_reg156_reg_lut56_low_mask ((1<<4)-1)
#define lut_reg156_reg_lut57_low_shift 0
#define lut_reg156_reg_lut57_low_mask ((1<<4)-1)

//#define lut_reg157_reg 0x19d
#define lut_reg157_reg_lut58_low_shift 4
#define lut_reg157_reg_lut58_low_mask ((1<<4)-1)
#define lut_reg157_reg_lut59_low_shift 0
#define lut_reg157_reg_lut59_low_mask ((1<<4)-1)

//#define lut_reg158_reg 0x19e
#define lut_reg158_reg_lut60_low_shift 4
#define lut_reg158_reg_lut60_low_mask ((1<<4)-1)
#define lut_reg158_reg_lut61_low_shift 0
#define lut_reg158_reg_lut61_low_mask ((1<<4)-1)

//#define lut_reg159_reg 0x19f
#define lut_reg159_reg_lut62_low_shift 4
#define lut_reg159_reg_lut62_low_mask ((1<<4)-1)
#define lut_reg159_reg_lut63_low_shift 0
#define lut_reg159_reg_lut63_low_mask ((1<<4)-1)

//#define fmcw_reg0_reg 0x200
#define fmcw_reg0_reg_rst_fmcw_n_bit (1<<7)
#define fmcw_reg0_reg_dsm_divn_negedge_bit (1<<6)
#define fmcw_reg0_reg_dsm_dither_2lsb_bit (1<<5)
#define fmcw_reg0_reg_dsm_dither_en_bit (1<<4)
#define fmcw_reg0_reg_dsm_dly_sel_bit (1<<3)
#define fmcw_reg0_reg_dsm_bypass_mash_bit (1<<2)
#define fmcw_reg0_reg_chirp_single_mode_bit (1<<1)
#define fmcw_reg0_reg_fmcw_en_bit (1<<0)

//#define fmcw_reg1_reg 0x201
#define fmcw_reg1_reg_dsm_int_dly_sel_shift 5
#define fmcw_reg1_reg_dsm_int_dly_sel_mask ((1<<3)-1)
#define fmcw_reg1_reg_test_divn_pad_mode_bit (1<<4)
#define fmcw_reg1_reg_test_clk_fmcw_divn_shift 2
#define fmcw_reg1_reg_test_clk_fmcw_divn_mask ((1<<2)-1)
#define fmcw_reg1_reg_test_clk_dsm_divn_shift 0
#define fmcw_reg1_reg_test_clk_dsm_divn_mask ((1<<2)-1)

//#define fmcw_reg4_reg 0x204
#define fmcw_reg4_reg_chirp_cycle_number_lsb_shift 0
#define fmcw_reg4_reg_chirp_cycle_number_lsb_mask ((1<<8)-1)

//#define fmcw_reg5_reg 0x205
#define fmcw_reg5_reg_chirp_cycle_number_msb_shift 0
#define fmcw_reg5_reg_chirp_cycle_number_msb_mask ((1<<8)-1)

//#define fmcw_reg6_reg 0x206
#define fmcw_reg6_reg_chirp_channel_num_shift 0
#define fmcw_reg6_reg_chirp_channel_num_mask ((1<<4)-1)

//#define fmcw_reg7_reg 0x207
#define fmcw_reg7_reg_fmcw_en_from_ds_bit (1<<7)
#define fmcw_reg7_reg_clk_ref_div2_sel_bit (1<<6)
#define fmcw_reg7_reg_clk_mmd_sel_ref_bit (1<<5)
#define fmcw_reg7_reg_clk_mmd_div2_sel_bit (1<<4)
#define fmcw_reg7_reg_clk_ref_inv_sel_bit (1<<3)
#define fmcw_reg7_reg_clk_ref_en_bit (1<<2)
#define fmcw_reg7_reg_clk_mmd_inv_sel_bit (1<<1)
#define fmcw_reg7_reg_clk_mmd_en_bit (1<<0)

//#define fmcw_reg8_reg 0x208
#define fmcw_reg8_reg_widen_bw_step_num_lsb_shift 0
#define fmcw_reg8_reg_widen_bw_step_num_lsb_mask ((1<<8)-1)

//#define fmcw_reg9_reg 0x209
#define fmcw_reg9_reg_widen_bw_step_num_msb_shift 0
#define fmcw_reg9_reg_widen_bw_step_num_msb_mask ((1<<8)-1)

//#define fmcw_reg10_reg 0x20a
#define fmcw_reg10_reg_widen_bw_channel_en_lsb_shift 0
#define fmcw_reg10_reg_widen_bw_channel_en_lsb_mask ((1<<8)-1)

//#define fmcw_reg11_reg 0x20b
#define fmcw_reg11_reg_widen_bw_channel_en_msb_shift 0
#define fmcw_reg11_reg_widen_bw_channel_en_msb_mask ((1<<8)-1)

//#define fmcw_reg12_reg 0x20c
#define fmcw_reg12_reg_freq_start_lsb_shift 0
#define fmcw_reg12_reg_freq_start_lsb_mask ((1<<8)-1)

//#define fmcw_reg13_reg 0x20d
#define fmcw_reg13_reg_freq_start_mid_shift 0
#define fmcw_reg13_reg_freq_start_mid_mask ((1<<8)-1)

//#define fmcw_reg14_reg 0x20e
#define fmcw_reg14_reg_freq_start_msb_shift 0
#define fmcw_reg14_reg_freq_start_msb_mask ((1<<7)-1)

//#define fmcw_reg16_reg 0x210
#define fmcw_reg16_reg_ch0_step_num_lsb_shift 0
#define fmcw_reg16_reg_ch0_step_num_lsb_mask ((1<<8)-1)

//#define fmcw_reg17_reg 0x211
#define fmcw_reg17_reg_ch0_step_num_mid_shift 0
#define fmcw_reg17_reg_ch0_step_num_mid_mask ((1<<8)-1)

//#define fmcw_reg18_reg 0x212
#define fmcw_reg18_reg_ch0_dt_step_lsb_shift 4
#define fmcw_reg18_reg_ch0_dt_step_lsb_mask ((1<<4)-1)
#define fmcw_reg18_reg_ch0_mode_shift 2
#define fmcw_reg18_reg_ch0_mode_mask ((1<<2)-1)
#define fmcw_reg18_reg_ch0_clear_bit (1<<1)
#define fmcw_reg18_reg_ch0_step_num_msb_bit (1<<0)

//#define fmcw_reg19_reg 0x213
#define fmcw_reg19_reg_ch0_df_step_lsb_shift 4
#define fmcw_reg19_reg_ch0_df_step_lsb_mask ((1<<4)-1)
#define fmcw_reg19_reg_ch0_dt_step_msb_shift 0
#define fmcw_reg19_reg_ch0_dt_step_msb_mask ((1<<4)-1)

//#define fmcw_reg20_reg 0x214
#define fmcw_reg20_reg_ch0_df_step_msb_shift 0
#define fmcw_reg20_reg_ch0_df_step_msb_mask ((1<<8)-1)

//#define fmcw_reg21_reg 0x215
#define fmcw_reg21_reg_ch1_step_num_lsb_shift 0
#define fmcw_reg21_reg_ch1_step_num_lsb_mask ((1<<8)-1)

//#define fmcw_reg22_reg 0x216
#define fmcw_reg22_reg_ch1_step_num_mid_shift 0
#define fmcw_reg22_reg_ch1_step_num_mid_mask ((1<<8)-1)

//#define fmcw_reg23_reg 0x217
#define fmcw_reg23_reg_ch1_dt_step_lsb_shift 4
#define fmcw_reg23_reg_ch1_dt_step_lsb_mask ((1<<4)-1)
#define fmcw_reg23_reg_ch1_mode_shift 2
#define fmcw_reg23_reg_ch1_mode_mask ((1<<2)-1)
#define fmcw_reg23_reg_ch1_clear_bit (1<<1)
#define fmcw_reg23_reg_ch1_step_num_msb_bit (1<<0)

//#define fmcw_reg24_reg 0x218
#define fmcw_reg24_reg_ch1_df_step_lsb_shift 4
#define fmcw_reg24_reg_ch1_df_step_lsb_mask ((1<<4)-1)
#define fmcw_reg24_reg_ch1_dt_step_msb_shift 0
#define fmcw_reg24_reg_ch1_dt_step_msb_mask ((1<<4)-1)

//#define fmcw_reg25_reg 0x219
#define fmcw_reg25_reg_ch1_df_step_msb_shift 0
#define fmcw_reg25_reg_ch1_df_step_msb_mask ((1<<8)-1)

//#define fmcw_reg26_reg 0x21a
#define fmcw_reg26_reg_ch2_step_num_lsb_shift 0
#define fmcw_reg26_reg_ch2_step_num_lsb_mask ((1<<8)-1)

//#define fmcw_reg27_reg 0x21b
#define fmcw_reg27_reg_ch2_step_num_mid_shift 0
#define fmcw_reg27_reg_ch2_step_num_mid_mask ((1<<8)-1)

//#define fmcw_reg28_reg 0x21c
#define fmcw_reg28_reg_ch2_dt_step_lsb_shift 4
#define fmcw_reg28_reg_ch2_dt_step_lsb_mask ((1<<4)-1)
#define fmcw_reg28_reg_ch2_mode_shift 2
#define fmcw_reg28_reg_ch2_mode_mask ((1<<2)-1)
#define fmcw_reg28_reg_ch2_clear_bit (1<<1)
#define fmcw_reg28_reg_ch2_step_num_msb_bit (1<<0)

//#define fmcw_reg29_reg 0x21d
#define fmcw_reg29_reg_ch2_df_step_lsb_shift 4
#define fmcw_reg29_reg_ch2_df_step_lsb_mask ((1<<4)-1)
#define fmcw_reg29_reg_ch2_dt_step_msb_shift 0
#define fmcw_reg29_reg_ch2_dt_step_msb_mask ((1<<4)-1)

//#define fmcw_reg30_reg 0x21e
#define fmcw_reg30_reg_ch2_df_step_msb_shift 0
#define fmcw_reg30_reg_ch2_df_step_msb_mask ((1<<8)-1)

//#define fmcw_reg31_reg 0x21f
#define fmcw_reg31_reg_ch3_step_num_lsb_shift 0
#define fmcw_reg31_reg_ch3_step_num_lsb_mask ((1<<8)-1)

//#define fmcw_reg32_reg 0x220
#define fmcw_reg32_reg_ch3_step_num_mid_shift 0
#define fmcw_reg32_reg_ch3_step_num_mid_mask ((1<<8)-1)

//#define fmcw_reg33_reg 0x221
#define fmcw_reg33_reg_ch3_dt_step_lsb_shift 4
#define fmcw_reg33_reg_ch3_dt_step_lsb_mask ((1<<4)-1)
#define fmcw_reg33_reg_ch3_mode_shift 2
#define fmcw_reg33_reg_ch3_mode_mask ((1<<2)-1)
#define fmcw_reg33_reg_ch3_clear_bit (1<<1)
#define fmcw_reg33_reg_ch3_step_num_msb_bit (1<<0)

//#define fmcw_reg34_reg 0x222
#define fmcw_reg34_reg_ch3_df_step_lsb_shift 4
#define fmcw_reg34_reg_ch3_df_step_lsb_mask ((1<<4)-1)
#define fmcw_reg34_reg_ch3_dt_step_msb_shift 0
#define fmcw_reg34_reg_ch3_dt_step_msb_mask ((1<<4)-1)

//#define fmcw_reg35_reg 0x223
#define fmcw_reg35_reg_ch3_df_step_msb_shift 0
#define fmcw_reg35_reg_ch3_df_step_msb_mask ((1<<8)-1)

//#define fmcw_reg36_reg 0x224
#define fmcw_reg36_reg_ch4_step_num_lsb_shift 0
#define fmcw_reg36_reg_ch4_step_num_lsb_mask ((1<<8)-1)

//#define fmcw_reg37_reg 0x225
#define fmcw_reg37_reg_ch4_step_num_mid_shift 0
#define fmcw_reg37_reg_ch4_step_num_mid_mask ((1<<8)-1)

//#define fmcw_reg38_reg 0x226
#define fmcw_reg38_reg_ch4_dt_step_lsb_shift 4
#define fmcw_reg38_reg_ch4_dt_step_lsb_mask ((1<<4)-1)
#define fmcw_reg38_reg_ch4_mode_shift 2
#define fmcw_reg38_reg_ch4_mode_mask ((1<<2)-1)
#define fmcw_reg38_reg_ch4_clear_bit (1<<1)
#define fmcw_reg38_reg_ch4_step_num_msb_bit (1<<0)

//#define fmcw_reg39_reg 0x227
#define fmcw_reg39_reg_ch4_df_step_lsb_shift 4
#define fmcw_reg39_reg_ch4_df_step_lsb_mask ((1<<4)-1)
#define fmcw_reg39_reg_ch4_dt_step_msb_shift 0
#define fmcw_reg39_reg_ch4_dt_step_msb_mask ((1<<4)-1)

//#define fmcw_reg40_reg 0x228
#define fmcw_reg40_reg_ch4_df_step_msb_shift 0
#define fmcw_reg40_reg_ch4_df_step_msb_mask ((1<<8)-1)

//#define fmcw_reg41_reg 0x229
#define fmcw_reg41_reg_ch5_step_num_lsb_shift 0
#define fmcw_reg41_reg_ch5_step_num_lsb_mask ((1<<8)-1)

//#define fmcw_reg42_reg 0x22a
#define fmcw_reg42_reg_ch5_step_num_mid_shift 0
#define fmcw_reg42_reg_ch5_step_num_mid_mask ((1<<8)-1)

//#define fmcw_reg43_reg 0x22b
#define fmcw_reg43_reg_ch5_dt_step_lsb_shift 4
#define fmcw_reg43_reg_ch5_dt_step_lsb_mask ((1<<4)-1)
#define fmcw_reg43_reg_ch5_mode_shift 2
#define fmcw_reg43_reg_ch5_mode_mask ((1<<2)-1)
#define fmcw_reg43_reg_ch5_clear_bit (1<<1)
#define fmcw_reg43_reg_ch5_step_num_msb_bit (1<<0)

//#define fmcw_reg44_reg 0x22c
#define fmcw_reg44_reg_ch5_df_step_lsb_shift 4
#define fmcw_reg44_reg_ch5_df_step_lsb_mask ((1<<4)-1)
#define fmcw_reg44_reg_ch5_dt_step_msb_shift 0
#define fmcw_reg44_reg_ch5_dt_step_msb_mask ((1<<4)-1)

//#define fmcw_reg45_reg 0x22d
#define fmcw_reg45_reg_ch5_df_step_msb_shift 0
#define fmcw_reg45_reg_ch5_df_step_msb_mask ((1<<8)-1)

//#define fmcw_reg46_reg 0x22e
#define fmcw_reg46_reg_ch6_step_num_lsb_shift 0
#define fmcw_reg46_reg_ch6_step_num_lsb_mask ((1<<8)-1)

//#define fmcw_reg47_reg 0x22f
#define fmcw_reg47_reg_ch6_step_num_mid_shift 0
#define fmcw_reg47_reg_ch6_step_num_mid_mask ((1<<8)-1)

//#define fmcw_reg48_reg 0x230
#define fmcw_reg48_reg_ch6_dt_step_lsb_shift 4
#define fmcw_reg48_reg_ch6_dt_step_lsb_mask ((1<<4)-1)
#define fmcw_reg48_reg_ch6_mode_shift 2
#define fmcw_reg48_reg_ch6_mode_mask ((1<<2)-1)
#define fmcw_reg48_reg_ch6_clear_bit (1<<1)
#define fmcw_reg48_reg_ch6_step_num_msb_bit (1<<0)

//#define fmcw_reg49_reg 0x231
#define fmcw_reg49_reg_ch6_df_step_lsb_shift 4
#define fmcw_reg49_reg_ch6_df_step_lsb_mask ((1<<4)-1)
#define fmcw_reg49_reg_ch6_dt_step_msb_shift 0
#define fmcw_reg49_reg_ch6_dt_step_msb_mask ((1<<4)-1)

//#define fmcw_reg50_reg 0x232
#define fmcw_reg50_reg_ch6_df_step_msb_shift 0
#define fmcw_reg50_reg_ch6_df_step_msb_mask ((1<<8)-1)

//#define fmcw_reg51_reg 0x233
#define fmcw_reg51_reg_ch7_step_num_lsb_shift 0
#define fmcw_reg51_reg_ch7_step_num_lsb_mask ((1<<8)-1)

//#define fmcw_reg52_reg 0x234
#define fmcw_reg52_reg_ch7_step_num_mid_shift 0
#define fmcw_reg52_reg_ch7_step_num_mid_mask ((1<<8)-1)

//#define fmcw_reg53_reg 0x235
#define fmcw_reg53_reg_ch7_dt_step_lsb_shift 4
#define fmcw_reg53_reg_ch7_dt_step_lsb_mask ((1<<4)-1)
#define fmcw_reg53_reg_ch7_mode_shift 2
#define fmcw_reg53_reg_ch7_mode_mask ((1<<2)-1)
#define fmcw_reg53_reg_ch7_clear_bit (1<<1)
#define fmcw_reg53_reg_ch7_step_num_msb_bit (1<<0)

//#define fmcw_reg54_reg 0x236
#define fmcw_reg54_reg_ch7_df_step_lsb_shift 4
#define fmcw_reg54_reg_ch7_df_step_lsb_mask ((1<<4)-1)
#define fmcw_reg54_reg_ch7_dt_step_msb_shift 0
#define fmcw_reg54_reg_ch7_dt_step_msb_mask ((1<<4)-1)

//#define fmcw_reg55_reg 0x237
#define fmcw_reg55_reg_ch7_df_step_msb_shift 0
#define fmcw_reg55_reg_ch7_df_step_msb_mask ((1<<8)-1)

//#define fmcw_reg56_reg 0x238
#define fmcw_reg56_reg_ch8_step_num_lsb_shift 0
#define fmcw_reg56_reg_ch8_step_num_lsb_mask ((1<<8)-1)

//#define fmcw_reg57_reg 0x239
#define fmcw_reg57_reg_ch8_step_num_mid_shift 0
#define fmcw_reg57_reg_ch8_step_num_mid_mask ((1<<8)-1)

//#define fmcw_reg58_reg 0x23a
#define fmcw_reg58_reg_ch8_dt_step_lsb_shift 4
#define fmcw_reg58_reg_ch8_dt_step_lsb_mask ((1<<4)-1)
#define fmcw_reg58_reg_ch8_mode_shift 2
#define fmcw_reg58_reg_ch8_mode_mask ((1<<2)-1)
#define fmcw_reg58_reg_ch8_clear_bit (1<<1)
#define fmcw_reg58_reg_ch8_step_num_msb_bit (1<<0)

//#define fmcw_reg59_reg 0x23b
#define fmcw_reg59_reg_ch8_df_step_lsb_shift 4
#define fmcw_reg59_reg_ch8_df_step_lsb_mask ((1<<4)-1)
#define fmcw_reg59_reg_ch8_dt_step_msb_shift 0
#define fmcw_reg59_reg_ch8_dt_step_msb_mask ((1<<4)-1)

//#define fmcw_reg60_reg 0x23c
#define fmcw_reg60_reg_ch8_df_step_msb_shift 0
#define fmcw_reg60_reg_ch8_df_step_msb_mask ((1<<8)-1)

//#define fmcw_reg61_reg 0x23d
#define fmcw_reg61_reg_ch9_step_num_lsb_shift 0
#define fmcw_reg61_reg_ch9_step_num_lsb_mask ((1<<8)-1)

//#define fmcw_reg62_reg 0x23e
#define fmcw_reg62_reg_ch9_step_num_mid_shift 0
#define fmcw_reg62_reg_ch9_step_num_mid_mask ((1<<8)-1)

//#define fmcw_reg63_reg 0x23f
#define fmcw_reg63_reg_ch9_dt_step_lsb_shift 4
#define fmcw_reg63_reg_ch9_dt_step_lsb_mask ((1<<4)-1)
#define fmcw_reg63_reg_ch9_mode_shift 2
#define fmcw_reg63_reg_ch9_mode_mask ((1<<2)-1)
#define fmcw_reg63_reg_ch9_clear_bit (1<<1)
#define fmcw_reg63_reg_ch9_step_num_msb_bit (1<<0)

//#define fmcw_reg64_reg 0x240
#define fmcw_reg64_reg_ch9_df_step_lsb_shift 4
#define fmcw_reg64_reg_ch9_df_step_lsb_mask ((1<<4)-1)
#define fmcw_reg64_reg_ch9_dt_step_msb_shift 0
#define fmcw_reg64_reg_ch9_dt_step_msb_mask ((1<<4)-1)

//#define fmcw_reg65_reg 0x241
#define fmcw_reg65_reg_ch9_df_step_msb_shift 0
#define fmcw_reg65_reg_ch9_df_step_msb_mask ((1<<8)-1)

//#define fmcw_reg66_reg 0x242
#define fmcw_reg66_reg_ch10_step_num_lsb_shift 0
#define fmcw_reg66_reg_ch10_step_num_lsb_mask ((1<<8)-1)

//#define fmcw_reg67_reg 0x243
#define fmcw_reg67_reg_ch10_step_num_mid_shift 0
#define fmcw_reg67_reg_ch10_step_num_mid_mask ((1<<8)-1)

//#define fmcw_reg68_reg 0x244
#define fmcw_reg68_reg_ch10_dt_step_lsb_shift 4
#define fmcw_reg68_reg_ch10_dt_step_lsb_mask ((1<<4)-1)
#define fmcw_reg68_reg_ch10_mode_shift 2
#define fmcw_reg68_reg_ch10_mode_mask ((1<<2)-1)
#define fmcw_reg68_reg_ch10_clear_bit (1<<1)
#define fmcw_reg68_reg_ch10_step_num_msb_bit (1<<0)

//#define fmcw_reg69_reg 0x245
#define fmcw_reg69_reg_ch10_df_step_lsb_shift 4
#define fmcw_reg69_reg_ch10_df_step_lsb_mask ((1<<4)-1)
#define fmcw_reg69_reg_ch10_dt_step_msb_shift 0
#define fmcw_reg69_reg_ch10_dt_step_msb_mask ((1<<4)-1)

//#define fmcw_reg70_reg 0x246
#define fmcw_reg70_reg_ch10_df_step_msb_shift 0
#define fmcw_reg70_reg_ch10_df_step_msb_mask ((1<<8)-1)

//#define fmcw_reg71_reg 0x247
#define fmcw_reg71_reg_ch11_step_num_lsb_shift 0
#define fmcw_reg71_reg_ch11_step_num_lsb_mask ((1<<8)-1)

//#define fmcw_reg72_reg 0x248
#define fmcw_reg72_reg_ch11_step_num_mid_shift 0
#define fmcw_reg72_reg_ch11_step_num_mid_mask ((1<<8)-1)

//#define fmcw_reg73_reg 0x249
#define fmcw_reg73_reg_ch11_dt_step_lsb_shift 4
#define fmcw_reg73_reg_ch11_dt_step_lsb_mask ((1<<4)-1)
#define fmcw_reg73_reg_ch11_mode_shift 2
#define fmcw_reg73_reg_ch11_mode_mask ((1<<2)-1)
#define fmcw_reg73_reg_ch11_clear_bit (1<<1)
#define fmcw_reg73_reg_ch11_step_num_msb_bit (1<<0)

//#define fmcw_reg74_reg 0x24a
#define fmcw_reg74_reg_ch11_df_step_lsb_shift 4
#define fmcw_reg74_reg_ch11_df_step_lsb_mask ((1<<4)-1)
#define fmcw_reg74_reg_ch11_dt_step_msb_shift 0
#define fmcw_reg74_reg_ch11_dt_step_msb_mask ((1<<4)-1)

//#define fmcw_reg75_reg 0x24b
#define fmcw_reg75_reg_ch11_df_step_msb_shift 0
#define fmcw_reg75_reg_ch11_df_step_msb_mask ((1<<8)-1)

//#define fmcw_fmcw_cyc_end 0x24c

//#define fmcw_fmcw_sync 0x24d
#define fmcw_fmcw_sync_adc_start_from_syncin_bit (1<<3)
#define fmcw_fmcw_sync_en_ckadc_from_syncin_bit (1<<2)
#define fmcw_fmcw_sync_negedge_sel_bit (1<<1)
#define fmcw_fmcw_sync_sync_out_bit (1<<0)

//#define fmcw_fmcw_sync_in 0x24e

//#define fmcw_mimo_ctrl 0x24f
#define fmcw_mimo_ctrl_auto_tx_psr_en_bit (1<<17)
#define fmcw_mimo_ctrl_auto_tx_on_en_bit (1<<16)
#define fmcw_mimo_ctrl_tx_psr_period_shift 8
#define fmcw_mimo_ctrl_tx_psr_period_mask ((1<<8)-1)
#define fmcw_mimo_ctrl_tx_on_period_shift 0
#define fmcw_mimo_ctrl_tx_on_period_mask ((1<<8)-1)

//#define fmcw_mimo_tx0_psr0 0x250

//#define fmcw_mimo_tx0_psr180 0x251

//#define fmcw_mimo_tx1_psr0 0x252

//#define fmcw_mimo_tx1_psr180 0x253

//#define fmcw_mimo_tx0_on 0x254

//#define fmcw_mimo_tx1_on 0x255

//#define fmcw_mimo_tx0_psr 0x256

//#define fmcw_mimo_tx1_psr 0x257

//#define mid_reg224_reg 0x2e0
#define mid_reg224_reg_manu_id0_shift 0
#define mid_reg224_reg_manu_id0_mask ((1<<8)-1)

//#define mid_reg225_reg 0x2e1
#define mid_reg225_reg_manu_id1_shift 0
#define mid_reg225_reg_manu_id1_mask ((1<<8)-1)

//#define mid_reg226_reg 0x2e2
#define mid_reg226_reg_manu_id2_shift 0
#define mid_reg226_reg_manu_id2_mask ((1<<8)-1)

//#define mid_reg227_reg 0x2e3
#define mid_reg227_reg_manu_id3_shift 0
#define mid_reg227_reg_manu_id3_mask ((1<<8)-1)

//#define pid_reg228_reg 0x2e4
#define pid_reg228_reg_prod_id0_shift 0
#define pid_reg228_reg_prod_id0_mask ((1<<8)-1)

//#define pid_reg229_reg 0x2e5
#define pid_reg229_reg_prod_id1_shift 0
#define pid_reg229_reg_prod_id1_mask ((1<<8)-1)

//#define fmcw_reg240_reg 0x2f0
#define fmcw_reg240_reg_reset_bank2_bit (1<<2)
#define fmcw_reg240_reg_reset_bank1_bit (1<<1)
#define fmcw_reg240_reg_reset_bank0_bit (1<<0)

// RFC 
typedef struct
{
  __IO uint32 rf_atn0_reg ;
  __IO uint32 rf_psr0_reg ;
  __IO uint32 rf_atn1_reg ;
  __IO uint32 rf_psr1_reg ;
  __IO uint32 rf_atn2_reg ;
  __IO uint32 rf_psr2_reg ;
  __IO uint32 rf_atn3_reg ;
  __IO uint32 rf_psr3_reg ;
  __IO uint32 rf_atn4_reg ;
  __IO uint32 rf_psr4_reg ;
  __IO uint32 rf_atn5_reg ;
  __IO uint32 rf_psr5_reg ;
  __IO uint32 rf_atn6_reg ;
  __IO uint32 rf_psr6_reg ;
  __IO uint32 rf_atn7_reg ;
  __IO uint32 rf_psr7_reg ;
  __IO uint32 rf_atn8_reg ;
  __IO uint32 rf_psr8_reg ;
  __IO uint32 rf_atn9_reg ;
  __IO uint32 rf_psr9_reg ;
  __IO uint32 rf_atn10_reg ;
  __IO uint32 rf_psr10_reg ;
  __IO uint32 rf_atn11_reg ;
  __IO uint32 rf_psr11_reg ;
  __IO uint32 rf_atn12_reg ;
  __IO uint32 rf_psr12_reg ;
  __IO uint32 rf_atn13_reg ;
  __IO uint32 rf_psr13_reg ;
  __IO uint32 rf_atn14_reg ;
  __IO uint32 rf_psr14_reg ;
  __IO uint32 rf_atn15_reg ;
  __IO uint32 rf_psr15_reg ;
  __IO uint32 rfc_nload_reg ;
       uint32 reserve0[2] ;
  __IO uint32 rf_atn_all_reg ;
  __IO uint32 rf_psr_all_reg ;
       uint32 reserve1[16] ;
  __IO uint32 rf_gpadc_data_reg ;
  __IO uint32 rf_gpadc_reg_reg ;
  __IO uint32 rf_adc0_data_reg ;
  __IO uint32 rf_adc0_regs_reg ;
       uint32 reserve2[4] ;
  __IO uint32 rf_adc1_data_reg ;
  __IO uint32 rf_adc1_regs_reg ;
       uint32 reserve3[3] ;
  __IO uint32 rf_bias1_en_reg ;
  __IO uint32 rf_rc32k_reg_reg ;
  __IO uint32 rf_bias1_regs_reg ;
  __IO uint32 rfc_bias1_dina_reg ;
  __IO uint32 rf_bias1_dinb_reg ;
  __IO uint32 rf_bias1_dinc_reg ;
  __IO uint32 rf_bias2_regs_reg ;
       uint32 reserve4[2] ;
  __IO uint32 rf_bias2_dina_reg ;
  __IO uint32 rf_bias2_dinb_reg ;
  __IO uint32 rf_bias2_dinc_reg ;
       uint32 reserve5[6] ;
  __IO uint32 rfc_xo50m_cfg_reg ;
  __IO uint32 rf_plli_ldo_cfg_reg ;
  __IO uint32 rf_plli_daca_reg ;
  __IO uint32 rf_plli_dacb_reg ;
  __IO uint32 rfc_plli_ctrl_reg ;
  __IO uint32 rf_plli_rega_reg ;
  __IO uint32 rf_plli_regb_reg ;
  __IO uint32 rf_plli_regc_reg ;
  __IO uint32 rf_plli_regd_reg ;
       uint32 reserve6[4] ;
  __IO uint32 rf_plln_rega_reg ;
  __IO uint32 rf_plln_regb_reg ;
  __IO uint32 rf_plln_regc_reg ;
  __IO uint32 rf_plln_regd_reg ;
  __IO uint32 rf_plln_rege_reg ;
  __IO uint32 rf_plln_ldo_cfg_reg ;
  __IO uint32 rf_plln_daca_reg ;
  __IO uint32 rf_plln_dacb_reg ;
  __IO uint32 rf_plln_ctrl_reg ;
       uint32 reserve7[4] ;
  __IO uint32 rfc_ldo_bg_reg_reg ;
  __IO uint32 rf_ldo18bb_regb_reg ;
  __IO uint32 rfc_ldo12n_rega_reg ;
       uint32 reserve8[16] ;
  __IO uint32 rf_buf20g_db_reg ;
  __IO uint32 rf_buf77g_ctrl_reg ;
  __IO uint32 rfc_tx_pa_reg ;
  __IO uint32 rfc_phase_shift_reg ;
  __IO uint32 rfc_rx_lna_reg ;
  __IO uint32 rfc_tia0_cfg_reg ;
  __IO uint32 rfc_tia1_cfg_reg ;
  __IO uint32 rfc_vga0_reg ;
  __IO uint32 rfc_vga1_reg ;
       uint32 reserve9[16] ;
  __IO uint32 rf_bist_cfg_reg ;
  __IO uint32 rf_bist_load ;
  __IO uint32 rf_bist_data_sync ;
  __IO uint32 rf_atb_cfg_reg ;
  __IO uint32 rf_spare_reg ;
       uint32 reserve10[97] ;
  __IO uint32 lut_reg0_reg ;
  __IO uint32 lut_reg1_reg ;
  __IO uint32 lut_reg2_reg ;
  __IO uint32 lut_reg3_reg ;
  __IO uint32 lut_reg4_reg ;
  __IO uint32 lut_reg5_reg ;
  __IO uint32 lut_reg6_reg ;
  __IO uint32 lut_reg7_reg ;
  __IO uint32 lut_reg8_reg ;
  __IO uint32 lut_reg9_reg ;
  __IO uint32 lut_reg10_reg ;
  __IO uint32 lut_reg11_reg ;
  __IO uint32 lut_reg12_reg ;
  __IO uint32 lut_reg13_reg ;
  __IO uint32 lut_reg14_reg ;
  __IO uint32 lut_reg15_reg ;
  __IO uint32 lut_reg16_reg ;
  __IO uint32 lut_reg17_reg ;
  __IO uint32 lut_reg18_reg ;
  __IO uint32 lut_reg19_reg ;
  __IO uint32 lut_reg20_reg ;
  __IO uint32 lut_reg21_reg ;
  __IO uint32 lut_reg22_reg ;
  __IO uint32 lut_reg23_reg ;
  __IO uint32 lut_reg24_reg ;
  __IO uint32 lut_reg25_reg ;
  __IO uint32 lut_reg26_reg ;
  __IO uint32 lut_reg27_reg ;
  __IO uint32 lut_reg28_reg ;
  __IO uint32 lut_reg29_reg ;
  __IO uint32 lut_reg30_reg ;
  __IO uint32 lut_reg31_reg ;
  __IO uint32 lut_reg32_reg ;
  __IO uint32 lut_reg33_reg ;
  __IO uint32 lut_reg34_reg ;
  __IO uint32 lut_reg35_reg ;
  __IO uint32 lut_reg36_reg ;
  __IO uint32 lut_reg37_reg ;
  __IO uint32 lut_reg38_reg ;
  __IO uint32 lut_reg39_reg ;
  __IO uint32 lut_reg40_reg ;
  __IO uint32 lut_reg41_reg ;
  __IO uint32 lut_reg42_reg ;
  __IO uint32 lut_reg43_reg ;
  __IO uint32 lut_reg44_reg ;
  __IO uint32 lut_reg45_reg ;
  __IO uint32 lut_reg46_reg ;
  __IO uint32 lut_reg47_reg ;
  __IO uint32 lut_reg48_reg ;
  __IO uint32 lut_reg49_reg ;
  __IO uint32 lut_reg50_reg ;
  __IO uint32 lut_reg51_reg ;
  __IO uint32 lut_reg52_reg ;
  __IO uint32 lut_reg53_reg ;
  __IO uint32 lut_reg54_reg ;
  __IO uint32 lut_reg55_reg ;
  __IO uint32 lut_reg56_reg ;
  __IO uint32 lut_reg57_reg ;
  __IO uint32 lut_reg58_reg ;
  __IO uint32 lut_reg59_reg ;
  __IO uint32 lut_reg60_reg ;
  __IO uint32 lut_reg61_reg ;
  __IO uint32 lut_reg62_reg ;
  __IO uint32 lut_reg63_reg ;
  __IO uint32 lut_reg64_reg ;
  __IO uint32 lut_reg65_reg ;
  __IO uint32 lut_reg66_reg ;
  __IO uint32 lut_reg67_reg ;
  __IO uint32 lut_reg68_reg ;
  __IO uint32 lut_reg69_reg ;
  __IO uint32 lut_reg70_reg ;
  __IO uint32 lut_reg71_reg ;
  __IO uint32 lut_reg72_reg ;
  __IO uint32 lut_reg73_reg ;
  __IO uint32 lut_reg74_reg ;
  __IO uint32 lut_reg75_reg ;
  __IO uint32 lut_reg76_reg ;
  __IO uint32 lut_reg77_reg ;
  __IO uint32 lut_reg78_reg ;
  __IO uint32 lut_reg79_reg ;
  __IO uint32 lut_reg80_reg ;
  __IO uint32 lut_reg81_reg ;
  __IO uint32 lut_reg82_reg ;
  __IO uint32 lut_reg83_reg ;
  __IO uint32 lut_reg84_reg ;
  __IO uint32 lut_reg85_reg ;
  __IO uint32 lut_reg86_reg ;
  __IO uint32 lut_reg87_reg ;
  __IO uint32 lut_reg88_reg ;
  __IO uint32 lut_reg89_reg ;
  __IO uint32 lut_reg90_reg ;
  __IO uint32 lut_reg91_reg ;
  __IO uint32 lut_reg92_reg ;
  __IO uint32 lut_reg93_reg ;
  __IO uint32 lut_reg94_reg ;
  __IO uint32 lut_reg95_reg ;
  __IO uint32 lut_reg96_reg ;
  __IO uint32 lut_reg97_reg ;
  __IO uint32 lut_reg98_reg ;
  __IO uint32 lut_reg99_reg ;
  __IO uint32 lut_reg100_reg ;
  __IO uint32 lut_reg101_reg ;
  __IO uint32 lut_reg102_reg ;
  __IO uint32 lut_reg103_reg ;
  __IO uint32 lut_reg104_reg ;
  __IO uint32 lut_reg105_reg ;
  __IO uint32 lut_reg106_reg ;
  __IO uint32 lut_reg107_reg ;
  __IO uint32 lut_reg108_reg ;
  __IO uint32 lut_reg109_reg ;
  __IO uint32 lut_reg110_reg ;
  __IO uint32 lut_reg111_reg ;
  __IO uint32 lut_reg112_reg ;
  __IO uint32 lut_reg113_reg ;
  __IO uint32 lut_reg114_reg ;
  __IO uint32 lut_reg115_reg ;
  __IO uint32 lut_reg116_reg ;
  __IO uint32 lut_reg117_reg ;
  __IO uint32 lut_reg118_reg ;
  __IO uint32 lut_reg119_reg ;
  __IO uint32 lut_reg120_reg ;
  __IO uint32 lut_reg121_reg ;
  __IO uint32 lut_reg122_reg ;
  __IO uint32 lut_reg123_reg ;
  __IO uint32 lut_reg124_reg ;
  __IO uint32 lut_reg125_reg ;
  __IO uint32 lut_reg126_reg ;
  __IO uint32 lut_reg127_reg ;
  __IO uint32 lut_reg128_reg ;
  __IO uint32 lut_reg129_reg ;
  __IO uint32 lut_reg130_reg ;
  __IO uint32 lut_reg131_reg ;
  __IO uint32 lut_reg132_reg ;
  __IO uint32 lut_reg133_reg ;
  __IO uint32 lut_reg134_reg ;
  __IO uint32 lut_reg135_reg ;
  __IO uint32 lut_reg136_reg ;
  __IO uint32 lut_reg137_reg ;
  __IO uint32 lut_reg138_reg ;
  __IO uint32 lut_reg139_reg ;
  __IO uint32 lut_reg140_reg ;
  __IO uint32 lut_reg141_reg ;
  __IO uint32 lut_reg142_reg ;
  __IO uint32 lut_reg143_reg ;
  __IO uint32 lut_reg144_reg ;
  __IO uint32 lut_reg145_reg ;
  __IO uint32 lut_reg146_reg ;
  __IO uint32 lut_reg147_reg ;
  __IO uint32 lut_reg148_reg ;
  __IO uint32 lut_reg149_reg ;
  __IO uint32 lut_reg150_reg ;
  __IO uint32 lut_reg151_reg ;
  __IO uint32 lut_reg152_reg ;
  __IO uint32 lut_reg153_reg ;
  __IO uint32 lut_reg154_reg ;
  __IO uint32 lut_reg155_reg ;
  __IO uint32 lut_reg156_reg ;
  __IO uint32 lut_reg157_reg ;
  __IO uint32 lut_reg158_reg ;
  __IO uint32 lut_reg159_reg ;
       uint32 reserve11[96] ;
  __IO uint32 fmcw_reg0_reg ;
  __IO uint32 fmcw_reg1_reg ;
       uint32 reserve12[2] ;
  __IO uint32 fmcw_reg4_reg ;
  __IO uint32 fmcw_reg5_reg ;
  __IO uint32 fmcw_reg6_reg ;
  __IO uint32 fmcw_reg7_reg ;
  __IO uint32 fmcw_reg8_reg ;
  __IO uint32 fmcw_reg9_reg ;
  __IO uint32 fmcw_reg10_reg ;
  __IO uint32 fmcw_reg11_reg ;
  __IO uint32 fmcw_reg12_reg ;
  __IO uint32 fmcw_reg13_reg ;
  __IO uint32 fmcw_reg14_reg ;
       uint32 reserve13[1] ;
  __IO uint32 fmcw_reg16_reg ;
  __IO uint32 fmcw_reg17_reg ;
  __IO uint32 fmcw_reg18_reg ;
  __IO uint32 fmcw_reg19_reg ;
  __IO uint32 fmcw_reg20_reg ;
  __IO uint32 fmcw_reg21_reg ;
  __IO uint32 fmcw_reg22_reg ;
  __IO uint32 fmcw_reg23_reg ;
  __IO uint32 fmcw_reg24_reg ;
  __IO uint32 fmcw_reg25_reg ;
  __IO uint32 fmcw_reg26_reg ;
  __IO uint32 fmcw_reg27_reg ;
  __IO uint32 fmcw_reg28_reg ;
  __IO uint32 fmcw_reg29_reg ;
  __IO uint32 fmcw_reg30_reg ;
  __IO uint32 fmcw_reg31_reg ;
  __IO uint32 fmcw_reg32_reg ;
  __IO uint32 fmcw_reg33_reg ;
  __IO uint32 fmcw_reg34_reg ;
  __IO uint32 fmcw_reg35_reg ;
  __IO uint32 fmcw_reg36_reg ;
  __IO uint32 fmcw_reg37_reg ;
  __IO uint32 fmcw_reg38_reg ;
  __IO uint32 fmcw_reg39_reg ;
  __IO uint32 fmcw_reg40_reg ;
  __IO uint32 fmcw_reg41_reg ;
  __IO uint32 fmcw_reg42_reg ;
  __IO uint32 fmcw_reg43_reg ;
  __IO uint32 fmcw_reg44_reg ;
  __IO uint32 fmcw_reg45_reg ;
  __IO uint32 fmcw_reg46_reg ;
  __IO uint32 fmcw_reg47_reg ;
  __IO uint32 fmcw_reg48_reg ;
  __IO uint32 fmcw_reg49_reg ;
  __IO uint32 fmcw_reg50_reg ;
  __IO uint32 fmcw_reg51_reg ;
  __IO uint32 fmcw_reg52_reg ;
  __IO uint32 fmcw_reg53_reg ;
  __IO uint32 fmcw_reg54_reg ;
  __IO uint32 fmcw_reg55_reg ;
  __IO uint32 fmcw_reg56_reg ;
  __IO uint32 fmcw_reg57_reg ;
  __IO uint32 fmcw_reg58_reg ;
  __IO uint32 fmcw_reg59_reg ;
  __IO uint32 fmcw_reg60_reg ;
  __IO uint32 fmcw_reg61_reg ;
  __IO uint32 fmcw_reg62_reg ;
  __IO uint32 fmcw_reg63_reg ;
  __IO uint32 fmcw_reg64_reg ;
  __IO uint32 fmcw_reg65_reg ;
  __IO uint32 fmcw_reg66_reg ;
  __IO uint32 fmcw_reg67_reg ;
  __IO uint32 fmcw_reg68_reg ;
  __IO uint32 fmcw_reg69_reg ;
  __IO uint32 fmcw_reg70_reg ;
  __IO uint32 fmcw_reg71_reg ;
  __IO uint32 fmcw_reg72_reg ;
  __IO uint32 fmcw_reg73_reg ;
  __IO uint32 fmcw_reg74_reg ;
  __IO uint32 fmcw_reg75_reg ;
  __IO uint32 fmcw_fmcw_cyc_end ;
  __IO uint32 fmcw_fmcw_sync ;
  __IO uint32 fmcw_fmcw_sync_in ;
  __IO uint32 fmcw_mimo_ctrl ;
  __IO uint32 fmcw_mimo_tx0_psr0 ;
  __IO uint32 fmcw_mimo_tx0_psr180 ;
  __IO uint32 fmcw_mimo_tx1_psr0 ;
  __IO uint32 fmcw_mimo_tx1_psr180 ;
  __IO uint32 fmcw_mimo_tx0_on ;
  __IO uint32 fmcw_mimo_tx1_on ;
  __IO uint32 fmcw_mimo_tx0_psr ;
  __IO uint32 fmcw_mimo_tx1_psr ;
       uint32 reserve14[136] ;
  __IO uint32 mid_reg224_reg ;
  __IO uint32 mid_reg225_reg ;
  __IO uint32 mid_reg226_reg ;
  __IO uint32 mid_reg227_reg ;
  __IO uint32 pid_reg228_reg ;
  __IO uint32 pid_reg229_reg ;
       uint32 reserve15[10] ;
  __IO uint32 fmcw_reg240_reg ;
}RFC_TypeDef;

#endif

